Storage system with data transfer rate adjustment for power throttling

• US 9,244,519 B1
• Filed: 06/25/2013
• Issued: 01/26/2016
• Est. Priority Date: 06/25/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Smart Storage Systems Incorporated (Western Digital Corporation)
• Inventors: Ellis, Robert W., Lucas, Gregg S., DelPapa, Kenneth B.
• Primary Examiner(s): Cao, Chun
• Application Number:
  US13/926,900
• Time in Patent Office: 945 Days
• Field of Search: 713/322, 713/340
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3253 Power saving in bus
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A storage control system, and a method of operation thereof, including: a host interface unit for receiving a host command from a host system; a power measurement hardware, coupled to the host interface unit, for reading a current value of electrical power supplied by the host system in response to the host command; and a power monitor controller, coupled to the power measurement hardware, for adjusting a bus speed for controlling data transfer through a channel shared by a number of non-volatile memory devices, the bus speed is adjusted based on the current value of the electrical power.

Claims

1. A method of operation of a storage system comprising:

at the storage system, receiving a host command from a host system, the host command comprising a write command;

at the storage system, in response to the host command, reading a current value of electrical power drawn by the storage system; and

at the storage system, in accordance with the current value of the electrical power drawn by the storage system, adjusting a bus speed for controlling a data transfer rate of one or more channels coupling a memory controller of the storage system to non-volatile memory devices of the storage system.

2. The method as claimed in claim 1 wherein adjusting the bus speed includes adjusting the bus speed based on comparison of the electrical power and a power limit register.

3. The method as claimed in claim 1 wherein adjusting the bus speed includes adjusting bus speeds based on the current value of the electrical power, one of the bus speeds is different from another of the bus speeds and for controlling the data transfer through the channel.

4. The method as claimed in claim 1 wherein the storage system includes a plurality of channels coupling the memory controller to the non-volatile memory devices, and the method further includes, at the storage system, in accordance with the current value of the electrical power drawn by the storage system, adjusting a number of parallel data transfer operations over the plurality of channels.

5. The method as claimed in claim 1 wherein adjusting the bus speed includes generating channel enable bits for controlling a number of channels based on the current value of the electrical power.

6. The method as claimed in claim 1, wherein adjusting the bus speed includes decreasing the bus speed when the current value of the electrical power is above a value in a power limit register and increasing the bus speed when the current value of the electrical power is below the value in the power limit register.

7. The method as claimed in claim 1, wherein the storage system includes a plurality of channels coupling the memory controller to the non-volatile memory devices, adjusting the bus speed includes adjusting bus speeds for two or more of the plurality of channels based on the current value of the electrical power, and one of the bus speeds is different from another of the bus speeds.

8. The method as claimed in claim 1, wherein adjusting the bus speed includes decreasing the bus speed when the current value of the electrical power is greater than a power limit and increasing the bus speed when the current value of the electrical power is less than a power floor.

9. The method as claimed in claim 1, wherein the storage system includes a plurality of channels coupling the memory controller to the non-volatile memory devices, adjusting the bus speed includes generating channel enable bits for controlling a number of the plurality of channels based on the current value of the electrical power, and a number of the channel enable bits equals the number of the channels.

10. A storage system comprising:

a host interface unit for receiving a host command from a host system, the host command comprising a write command;

power measurement hardware, coupled to the host interface unit, for reading a current value of electrical power drawn by the storage system in response to the host command; and

a power monitor controller, coupled to the power measurement hardware, for adjusting a bus speed for controlling, in accordance with the current value of the electrical power drawn by the storage system, a data transfer rate of one or more channels coupling a memory controller of the storage system to non-volatile memory devices of the storage system.

11. The system as claimed in claim 10 wherein the power monitor controller is for adjusting the bus speed based on comparison of the electrical power and a power limit register.

12. The system as claimed in claim 10 wherein the power monitor controller is for adjusting bus speeds based on the current value of the electrical power, one of the bus speeds is different from another of the bus speeds and for controlling the data transfer through the channel.

13. The system as claimed in claim 10 wherein the storage system includes a plurality of channels coupling the memory controller to the non-volatile memory devices, and the power monitor controller is for adjusting a number of parallel data transfer operations over the plurality of channels in accordance with the current value of the electrical power drawn by the storage system.

14. The system as claimed in claim 10 wherein the power monitor controller is for generating channel enable bits for controlling a number of channels based on the current value of the electrical power.

15. The system as claimed in claim 10 wherein the power measurement hardware is for reading the current value of the electrical power measured based on a sensed current.

16. The system as claimed in claim 10, wherein the power monitor controller is for decreasing the bus speed when the current value of the electrical power is above a value in a power limit register and increasing the bus speed when the current value of the electrical power is below the value in the power limit register.

17. The system as claimed in claim 10, wherein the storage system includes a plurality of channels coupling the memory controller to the non-volatile memory devices, the power monitor controller is for adjusting bus speeds for two or more of the plurality of channels based on the current value of the electrical power, and one of the bus speeds is different from another of the bus speeds.

18. The system as claimed in claim 10, wherein the power monitor controller is for decreasing the bus speed when the current value of the electrical power is greater than a power limit and increasing the bus speed when the current value of the electrical power is less than a power floor.

19. The system as claimed in claim 10, wherein the storage system includes a plurality of channels coupling the memory controller to the non-volatile memory devices, the power monitor controller is for generating channel enable bits for controlling a number of the plurality of channels based on the current value of the electrical power, and a number of the channel enable bits equals the number of the channels.