Energy-focused compiler-assisted branch prediction

• US 9,244,689 B2
• Filed: 12/05/2013
• Issued: 01/26/2016
• Est. Priority Date: 02/04/2004
• Status: Active Grant

• Current Assignee: III Holdings 2, LLC
• Original Assignee: III Holdings 2, LLC
• Inventors: Chheda, Saurabh, Carver, Kristopher, Ashok, Raksit
• Primary Examiner(s): Wong, Don
• Assistant Examiner(s): Lee, Marina
• Application Number:
  US14/097,879
• Publication Number:
  US 20140173262A1
• Time in Patent Office: 782 Days
• Field of Search: 717120-131, 717207-212, 717/158
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3846 using static prediction, e.g. branch taken strategy
• CPC Class Codes: G06F 9/3848 using hybrid branch prediction, e.g. selection between prediction techniques

Abstract

A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Claims

1. A method for use with a processor, the method comprising:

with respect to an instruction sequence including a control-flow changing instruction to affect a control-flow of the instruction sequence;

adding control information to the instruction sequence; and

removing the control-flow changing instruction from the instruction sequence;

wherein the control information is to be utilized at runtime to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path.

2. The method of claim 1, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

3. The method of claim 1, wherein the control information comprises part of a payload of a coprocessor instruction.

4. The method of claim 1, wherein the control information comprises code for selecting a dynamic branch prediction mechanism at runtime.

5. The method of claim 1, wherein the control information is configured to stall fetching at runtime until another control-flow changing instruction is executed that is not predictable statically or dynamically.

6. The method of claim 1, wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

7. The method of claim 1, further comprising:

performing an analysis of the instruction sequence at compile time in order to generate the control information.

8. The method of claim 1, wherein the control information identifies a position associated with the control-flow changing instruction in the instruction sequence.

9. The method of claim 1, wherein the control information specifies a condition under which a control-flow change at an end of the instruction sequence should occur.

19. The method of claim 1, wherein the position precedes a position originally occupied by the control-flow changing instruction.

20. The method of claim 1, wherein the position is the same as a position originally occupied by the control-flow changing instruction.

10. A system for use with a processor, the system comprising:

microarchitecture to access control information of an instruction sequence at runtime, the control information added at a position in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime; and

the microarchitecture to use the control information to predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction, and to fetch an instruction corresponding to the path, the microarchitecture comprising hardware.

11. The system of claim 10, wherein the control information comprises part of an instruction configured to affect at least one of processor efficiency or processor energy consumption.

12. The system of claim 10, wherein the control information comprises part of a payload of a coprocessor instruction.

13. The system of claim 10, wherein the control information includes static instructions, and wherein the microarchitecture is configured to remove the static instructions in a prefetch buffer at runtime to prevent the static instructions from entering the pipeline of the processor.

14. The system of claim 10, wherein the control information comprises code for selecting a dynamic branch prediction mechanism at runtime.

15. The system of claim 10, wherein responsive to using the control information fetching is stalled until execution of another control-flow changing instruction that is not predictable statically or dynamically.

16. The system of claim 10, wherein the control information comprises static information that suggests at least one of plural dynamic prediction mechanisms.

17. The system of claim 10, wherein the control information identifies a position associated with the control-flow changing instruction in the instruction sequence.

18. The system of claim 10, wherein the outcome of the control-flow changing instruction is coded in the control information.

21. A method for use with a processor, the method comprising:

with respect to control information of an instruction sequence, the control information added at a position in the instruction sequence prior to runtime to prevent coded information corresponding to a control-flow changing instruction from being decoded in a pipeline of the processor at runtime, using the control information at runtime to;

predict an outcome of the control-flow changing instruction, the outcome comprising a target of the control-flow changing instruction that includes a path following the control-flow changing instruction; and

fetch an instruction corresponding to the path.

22. The method of claim 21, wherein the control information comprises at least one of:

part of an instruction configured to affect at least one of processor efficiency or processor energy consumption;

part of a payload of a coprocessor instruction;

code for selecting a dynamic branch prediction mechanism at runtime;

static information that suggests at least one of plural dynamic prediction mechanisms;

or

code for specifying a condition under which a control-flow change at an end of the instruction sequence should occur.