Management of transactional memory access requests by a cache memory

• US 9,244,724 B2
• Filed: 08/15/2013
• Issued: 01/26/2016
• Est. Priority Date: 08/15/2013
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Ghai, Sanjeev, Guthrie, Guy L., Jackson, Jonathan R., Williams, Derek E.
• Primary Examiner(s): Verbrugge, Kevin
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US13/967,795
• Publication Number:
  US 20150052315A1
• Time in Patent Office: 894 Days
• Field of Search: 711/145
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence

Abstract

In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

Claims

1. A processing unit for a data processing system including a shared memory system, the processing unit comprising:

a processor core; and

a cache memory coupled to the processor core, the cache memory including;

a cache array;

a directory;

read-claim logic that services memory access requests of the processor core; and

dispatch logic that, responsive to receiving a transactional memory access request issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing a current execution by the processor core, evaluates the transactional memory access request for dispatch to the read-claim logic for service by determining whether the memory transaction has a failing transaction state, and wherein the dispatch logic, responsive to determining the memory transaction has a failing transaction state, refrains from dispatching the memory access request for service by the read-claim logic during the current execution of the memory transaction and refrains from updating at least replacement order information in the directory in response to the transactional memory access request during the current execution of the memory transaction.

2. The processing unit of claim 1, wherein:

the transactional memory access request is a transactional load request; and

the dispatch logic, responsive to determining the memory transaction has a failing transaction state, causes the cache memory to transmit a transactional memory abort code to the processor core in lieu of data requested by the transactional load request.

3. The processing unit of claim 1, wherein:

the transactional memory access request is a transactional store request; and

the dispatch logic, responsive to determining the memory transaction has a failing transaction state, discards the store request.

4. The processing unit of claim 1, wherein the dispatch logic, responsive to determining the memory transaction has a running transaction state, dispatches the transactional memory access request subject to dispatch criteria for non-transactional memory access requests.

5. The processing unit of claim 1, wherein:

the memory transaction is within a first thread;

the cache memory further comprises;

transactional memory tracking logic coupled to the dispatch logic, wherein the transactional memory tracking logic determines the transaction state of the memory transaction by reference to a transaction footprint of the memory transaction and memory access requests of one or more other simultaneously executing threads, and wherein the transactional memory tracking logic provides a transaction state indication indicating the determined transaction state to the dispatch logic.

6. The processing unit of claim 5, wherein:

the determined transaction state is the failing state; and

the transactional memory tracking logic updates the transaction state of the memory transaction to the failing state in response to a memory access request by one of the one or more other simultaneously executing threads.

7. A data processing system, comprising:

a plurality of processing units in accordance with claim 1; and

an interconnect fabric coupling the plurality of processing units.

8. A design structure tangibly embodied in a machine-readable storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit for a data processing system including a shared memory system, the processing unit including;

a processor core; and

a cache memory coupled to the processor core, the cache memory including;

a cache array;

a directory;

read-claim logic that services memory access requests of the processor core; and

dispatch logic that, responsive to receiving a transactional memory access request issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing a current execution by the processor core, evaluates the transactional memory access request for dispatch to the read-claim logic for service by determining whether the memory transaction has a failing transaction state, and wherein the dispatch logic, responsive to determining the memory transaction has a failing transaction state, refrains from dispatching the memory access request for service by the read-claim logic during the current execution of the memory transaction and refrains from updating at least replacement order information in the directory in response to the transactional memory access request during the current execution of the memory transaction.

9. The design structure of claim 8, wherein:

the transactional memory access request is a transactional load request; and

the dispatch logic, responsive to determining the memory transaction has a failing transaction state, causes the cache memory to transmit a transactional memory abort code to the processor core in lieu of data requested by the transactional load request.

10. The design structure of claim 8, wherein:

the transactional memory access request is a transactional store request; and

the dispatch logic, responsive to determining the memory transaction has a failing transaction state, discards the store request.

11. The design structure of claim 8, wherein the dispatch logic, responsive to determining the memory transaction has a running transaction state, dispatches the transactional memory access request subject to dispatch criteria for non-transactional memory access requests.

12. The design structure of claim 8, wherein:

the memory transaction is within a first thread;

the cache memory further comprises;

transactional memory tracking logic coupled to the dispatch logic, wherein the transactional memory tracking logic determines the transaction state of the memory transaction by reference to a transaction footprint of the memory transaction and memory access requests of one or more other simultaneously executing threads, and wherein the transactional memory tracking logic provides a transaction state indication indicating the determined transaction state to the dispatch logic.

13. The design structure of claim 12, wherein:

the determined transaction state is the failing state; and

the transactional memory tracking logic updates the transaction state of the memory transaction to the failing state in response to a memory access request by one of the one or more other simultaneously executing threads.

14. The design structure of claim 8, wherein the design structure comprises a hardware description language (HDL) design structure.