System and method for updating a reading threshold voltage based on symbol transition information

• US 9,244,763 B1
• Filed: 09/17/2013
• Issued: 01/26/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Kankani, Navneeth, Kwong, Charles See Yeung
• Primary Examiner(s): Chung, Phung M
• Application Number:
  US14/029,694
• Time in Patent Office: 861 Days
• Field of Search: 714/E11.034, 714/763, 714/764, 714/42, 714/746, 714/768, 711/E12.008, 711/E12.001, 365/185.22, 365/185.33, 365/210.12
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. The method includes obtaining symbol transition information corresponding to symbol read errors identified while reading data from flash memory cells in a flash memory device. The method further includes determining a reading threshold voltage offset, based at least in part on: a plurality of probability values determined from the symbol transition information; a current count of program-erase cycles; and a word line zone value for a word line zone containing the flash memory cells. Additionally, the method includes generating an updated reading threshold voltage in accordance with the reading threshold voltage offset and the current value of the reading threshold voltage.

Claims

1. A method for updating a reading threshold voltage applied to control gates of memory cells in a flash memory device while reading symbols from the flash memory device, the method comprising:

in response to one or more first host read commands received from a host device, obtaining symbol transition information corresponding to symbol read errors identified while reading data from flash memory cells in the flash memory device in accordance with the one or more first host read commands and the current value of the reading threshold voltage;

determining a reading threshold voltage offset, based at least in part on;

a first factor based on a plurality of probability values determined from the symbol transition information;

a second factor based on a current count of program-erase cycles; and

a third factor based on a word line zone value for a word line zone of the flash memory device containing the flash memory cells from which the data was read in response to the one or more first host read commands;

generating an updated reading threshold voltage, to be applied to the control gates of memory cells in the flash memory device while reading symbols from the flash memory device, in accordance with the reading threshold voltage offset and the current value of the reading threshold voltage; and

in response to one or more second host read commands, different from the one or more first host read commands received from the host device, reading data from the flash memory cells in accordance with the one or more second host read commands and the updated reading threshold voltage.

2. The method of claim 1, wherein obtaining symbol transition information includes obtaining symbol transition information for a set of reference cells in respective codewords of the data read in response to the one or more first host read commands.

3. The method of claim 2, wherein the set of reference cells of each respective codeword contains n·

2ⁿ bits of information, where n is the number of bits stored per flash memory cell.

4. The method of claim 1, wherein obtaining symbol transition information includes receiving corrected read data from an ECC decoder and corresponding raw data read in response to the one or more first host read commands.

5. The method of claim 4, wherein the read data is collected during a read patrol operation.

6. The method of claim 1, comprising determining the reading threshold voltage offset every X program-erase cycles, wherein X is an integer.

7. The method of claim 1, further comprising determining a plurality of reading threshold voltage offsets, wherein the plurality of reading threshold voltage offsets is equal to 2ⁿ−

1 reading threshold voltage offsets, where n is the number of bits stored per flash memory cell.

8. The method of claim 1, wherein the first factor is based on a ratio of a first set of probability values determined from a first set of symbol transition information to a second set of a probability values determined from a second set of symbol transition information, wherein the second set of symbol transition information was generated at time T-2 and the first set of symbol transition information is generated at time T-1.

9. The method of claim 1, wherein the second factor is based on a cumulative count of program-erase cycles for the flash memory device or a predefined portion of the flash memory device.

10. The method of claim 1, wherein the flash memory device includes a plurality of word line zones.

11. The method of claim 10, comprising generating an updated reading threshold voltage for each of the plurality of word line zones.

12. A controller for updating a reading threshold voltage applied to control gates of memory cells in a flash memory device while reading symbols from the flash memory device, the controller comprising:

a memory controller with interfaces to the flash memory device and a host, configured to;

in response to one or more first host read commands received from a host device, obtain symbol transition information corresponding to symbol read errors identified while reading data from flash memory cells in the flash memory device in accordance with the one or more first host read commands and the current value of the reading threshold voltage;

determine a reading threshold voltage offset, based at least in part on;

a first factor based on a plurality of probability values determined from the symbol transition information;

a second factor based on a current count of program-erase cycles; and

a third factor based on a word line zone value for a word line zone of the flash memory device containing the flash memory cells from which data was read in response to the first host read commands;

generate an updated reading threshold voltage, to be applied to the control gates of memory cells in the flash memory device while reading symbols from the flash memory device, in accordance with the reading threshold voltage offset and the current value of the reading threshold voltage; and

in response to one or more second host read commands, different from the one or more first host read commands received from the host device, read data from the flash memory cells in accordance with the one or more second host read commands and the updated reading threshold voltage.

13. The controller of claim 12, wherein the memory controller is configured to obtain symbol transition information by obtaining symbol transition information for a set of reference cells in respective codewords of the data read in response to the one or more first host read commands.

14. The controller of claim 13, wherein the set of reference cells of each respective codeword contains n·

2ⁿ bits of information, where n is the number of bits stored per flash memory cell.

15. The controller of claim 12, wherein the memory controller is configured to obtain symbol transition information by receiving corrected read data from an ECC decoder and corresponding raw data read in response to the one or more first host read commands.

16. The controller of claim 15, wherein the read data is collected during a read patrol operation.

17. The controller of claim 12, wherein the memory controller is configured to determine the reading threshold voltage offset every X program-erase cycles, wherein X is an integer.

18. The controller of claim 12, wherein the memory controller is further configured to determine a plurality of reading threshold voltage offsets, wherein the plurality of reading threshold voltage offsets is equal to 2ⁿ−

1 reading threshold voltage offsets, where n is the number of bits stored per flash memory cell.

19. The controller of claim 12, wherein the first factor is based on a ratio of a first set of probability values determined from a first set of symbol transition information to a second set of a probability values determined from a second set of symbol transition information, wherein the second set of symbol transition information was generated at time T-2 and the first set of symbol transition information is generated at time T-1.

20. The controller of claim 12, wherein the second factor is based on a cumulative count of program-erase cycles for the flash memory device or a predefined portion of the flash memory device.

21. The controller of claim 12, wherein the flash memory device includes a plurality of word line zones.

22. The controller of claim 21, wherein the memory controller is configured to generate an updated reading threshold voltage for each of the plurality of word line zones.