Error correcting code techniques for a memory having a three-dimensional memory configuration

• US 9,244,764 B2
• Filed: 05/08/2014
• Issued: 01/26/2016
• Est. Priority Date: 05/08/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: D'Abreu, Manuel Antonio, Hu, Xinde
• Primary Examiner(s): Chase, Shelly A
• Application Number:
  US14/273,005
• Publication Number:
  US 20150324251A1
• Time in Patent Office: 628 Days
• Field of Search: 714/708, 714/746, 714/774, 714/773
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check

Abstract

A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes encoding first data to be stored at a first physical page. The first physical page is disposed within the memory at a first distance from a substrate of the memory, and the first data is encoded using a first encoding technique. The method further includes encoding second data to be stored at a second physical page. The second physical page is disposed within the memory at a second distance from the substrate that is greater than the first distance. The second data is encoded using a second encoding technique that is different than the first encoding technique.

Claims

1. A method comprising:

in a data storage device that includes a memory having a three-dimensional (3D) memory configuration, performing;

encoding first data to be stored at a first physical page that is disposed within the memory at a first distance from a substrate of the memory, wherein the first data is encoded using a first encoding technique; and

encoding second data to be stored at a second physical page that is disposed within the memory at a second distance from the substrate, wherein the second distance is greater than the first distance, and wherein the second data is encoded using a second encoding technique that is different than the first encoding technique.

2. The method of claim 1, further comprising storing an error correcting code (ECC) parameter table at the data storage device, wherein the ECC parameter table indicates a first ECC parameter for a first set of one or more physical pages of the memory and further indicates a second ECC parameter for a second set of one or more physical pages of the memory.

3. The method of claim 2, wherein the distance defines a location, wherein the first set is disposed below the location, wherein the second set is disposed above the location, and wherein the location is associated with a variation in a structure of the memory that extends through multiple layers of the memory.

4. The method of claim 2, further comprising:

prior to encoding the first data and the second data, accessing a logical-to-physical address mapping table to determine that the first data is to be stored at the first physical page and that the second data is to be stored at the second physical page; and

in response to determining that the first data is to be stored at the first physical page and that the second data is to be stored at the second physical page, accessing the ECC parameter table to determine that the first data is to be encoded using the first encoding technique and that the second data is to be encoded using the second encoding technique.

5. The method of claim 4, further comprising changing a mode of operation of an ECC engine of the data storage device from using the first encoding technique to the second encoding technique prior to encoding the second data and in response to determining that the second data is to be stored at the second physical page.

6. The method of claim 1, wherein encoding the first data generates a first error correcting code (ECC) codeword, wherein encoding the second data generates a second ECC codeword, and further comprising:

storing the first ECC codeword at the first physical page; and

storing the second ECC codeword at the second physical page.

7. The method of claim 6, further comprising:

receiving one or more requests from a host device for read access to the first data and to the second data; and

in response to the one or more requests;

sensing the first ECC codeword from the first physical page; and

sensing the second ECC codeword from the second physical page.

8. The method of claim 7, further comprising:

decoding the first ECC codeword using a first decoding technique to generate the first data; and

decoding the second ECC codeword to generate the second data using a second decoding technique that is different than the first decoding technique.

9. The method of claim 8, further comprising:

prior to decoding the first data and the second data, accessing a logical-to-physical address mapping table to determine that the first data is stored at the first physical page and that the second data is stored at the second physical page; and

accessing an ECC parameter table to determine that the first ECC codeword is to be decoded using a first decoding technique and that the second data is to be decoded using a second decoding technique.

10. The method of claim 9, further comprising changing a mode of operation of an ECC engine of the data storage device from using the first decoding technique to the second decoding technique prior to decoding the second data and in response to determining that the second data is to be decoded using the second decoding technique.

11. The method of claim 6, wherein the first ECC codeword has a first number of ECC bits, and wherein the second ECC codeword has a second number of ECC bits that is greater than the first number of ECC bits.

12. The method of claim 1, wherein the first encoding technique is a polynomial-based encoding technique, and where the second encoding technique is a probabilistic-based encoding technique.

13. The method of claim 1, wherein the first encoding technique includes a Bose-Chaudhuri-Hocquenghem (BCH) encoding technique, and wherein the second encoding technique includes one of a low-density parity check (LDPC) technique or a turbo coding technique.

14. The method of claim 1, wherein the data storage device further includes a controller that is operationally coupled to the memory, and wherein the controller encodes the first data and the second data.

15. The method of claim 1, wherein the memory is a non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and wherein the data storage device further includes circuitry associated with operation of the memory cells.

16. A data storage device comprising:

a memory having a three-dimensional (3D) memory configuration, wherein the memory includes a substrate, a first physical page that is disposed within the memory at a first distance from the substrate, and a second physical page that is disposed within the memory at a second distance from the substrate, wherein the second distance is greater than the first distance; and

a controller coupled to the memory, wherein the controller is configured to encode first data to be stored at the first physical page using a first encoding technique, and wherein the controller is further configured to encode second data to be stored at the second physical page using a second encoding technique that is different than the first encoding technique.

17. The data storage device of claim 16, wherein an error correcting code (ECC) parameter table is stored at the memory, and wherein the ECC parameter table indicates a first ECC parameter for a first set of one or more physical pages of the memory and further indicating a second ECC parameter for a second set of one or more physical pages of the memory.

18. The data storage device of claim 17, wherein the distance defines a location, wherein the first set is disposed below the location, wherein the second set is disposed above the location, and wherein the location is associated with a variation in a structure of the memory that extends through multiple layers of the memory.

19. The data storage device of claim 17, wherein the controller is further configured to access a logical-to-physical address mapping table to determine that the first data is to be stored at the first physical page and that the second data is to be stored at the second physical page and to further determine that the first data is to be encoded using the first encoding technique and that the second data is to be encoded using the second encoding technique.

20. The data storage device of claim 16, wherein the memory is a non-volatile memory that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate, and further comprising circuitry associated with operation of the memory cells.