Variable data recovery scheme hierarchy

• US 9,244,766 B2
• Filed: 09/23/2013
• Issued: 01/26/2016
• Est. Priority Date: 09/23/2013
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Patapoutian, Ara, Buch, Bruce Douglas, Goss, Ryan James, Gaertner, Mark Allen, Sridharan, Arvind
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US14/034,251
• Publication Number:
  US 20150089278A1
• Time in Patent Office: 855 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.

Claims

1. An apparatus comprising:

a memory comprising a plurality of solid-state non-volatile memory cells; and

a processing circuit connected to the memory and configured to direct execution of a plurality of read error recovery routines responsive to at least one uncorrectable read error in a data set retrieved from the memory, the recovery routines executed in a selected order based on an elapsed recovery time parameter for each the recovery routines and an estimated probability of success for each of the recovery routines, the processing circuit further configured to generate and store in a local memory a correction table that lists the plurality of read error recovery routines in the selected order, the processing circuit further configured to measure an elapsed time interval during which each of the read error recovery routines is executed and to record, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error.

2. The apparatus of claim 1, further comprising a read circuit configured to, responsive to a read command, retrieve the data set from the memory and apply parity data to the retrieved data set in an attempt to detect and correct bit errors therein, wherein at least one uncorrectable error is present in the retrieved data set at a conclusion of the application of the parity data.

3. The apparatus of claim 2, wherein the parity data comprises error correction codes selected in relation to a measured bit error rate of data read from the memory, wherein different types of parity data are applied responsive to changes in the measured bit error rate over an operational life of the memory.

4. The apparatus of claim 1, wherein the processing circuit establishes the selected order responsive to an elapsed time interval associated with each of the plurality of read error recovery routines and a probability of success of each of the plurality of read error recovery routines.

5. The apparatus of claim 4, wherein the processing circuit subsequently rearranges the plurality of read error recovery routines into a new, different order responsive to a subsequently measured elapsed time interval associated with each of the plurality of read error recovery routines and a subsequently determined probability of success of each of the plurality of read error recovery routines.

6. The apparatus of claim 1, wherein the plurality of read error recovery routines includes a read retry routine wherein a read retry operation is carried out at least once using a baseline read threshold, a soft decode routine wherein an adjusted read threshold is applied in an attempt to decode the data set, and an iterative read data error recovery approach is applied up to a maximum number of iterations.

7. The apparatus of claim 1, wherein the correction table is a global correction table comprising a first ordering of read error recovery routines and the processing circuit further generates and stores a local correction table comprising a different, second ordering of read error recovery routines, wherein the processing circuit further applies the different, second ordering of read error recovery routines in the local correction table responsive to a second unrecoverable read error and a measured parameter associated with the memory.

8. The apparatus of claim 7, wherein the measured parameter comprises a workload associated with the memory.

9. The apparatus of claim 7, wherein the measured parameter comprises a bit placement of a page of memory in a row of memory cells.

10. The apparatus of claim 7, wherein the measured parameter comprises an address of the retrieved data set in the memory.

11. The apparatus of claim 1, wherein the memory comprises a flash memory and the processing circuit comprises a programmable processor that uses programming steps stored in a memory device to carry out the respective recovery routines.

12. A method comprising:

storing data to a memory comprising a plurality of solid-state non-volatile memory cells;

performing a read operation to subsequently retrieve the data from the memory by applying parity data to a user data payload portion of the data to detect and correct up to a selected number of errors, wherein at a conclusion of said application of the parity data at least one uncorrectable read error remains in the retrieved data; and

implementing a read error recovery routine to resolve the at least one uncorrectable read error by executing a plurality of read error recovery routines in a selected order based on an elapsed recovery time parameter to complete each of the recovery routines and an estimated probability of success of each of the recovery routines, the elapsed time recovery parameter comprising a first average time to successfully complete the associated recovery routine where a read error is successfully corrected, and a second average time to complete the associated recovery routine where said routine is unsuccessful in correcting a read error.

13. The method of claim 12, wherein the performing a read operation comprises applying error correction codes to the user data payload portion selected in relation to a measured bit error rate, wherein different strengths of the error correction codes are applied responsive to changes in the measured bit error rate over an operational life of the memory.

14. The method of claim 12, wherein the implementing a read error recovery routine comprises generating and storing, in a local memory, a correction table which lists the plurality of read error recovery routines in the selected order.

15. The method of claim 14, wherein the implementing a read error recovery routine further comprises measuring an elapsed time interval during which each of the read error recovery routines is executed and recording, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error.

16. The method of claim 12, wherein the selected order is determined responsive to an elapsed time interval associated with each of the plurality of read error recovery routines and a probability of success of each of the plurality of read error recovery routines.

17. The method of claim 12, wherein the plurality of read error recovery routines includes a read retry routine wherein a read retry operation is carried out at least once, a soft decode routine wherein non-standard read thresholds are applied in an attempt to decode the data set, and an iterative read data error recovery approach is applied up to a maximum number of iterations.

18. A storage device comprising:

a memory comprising a plurality of solid-state non-volatile memory cells; and

a processing circuit connected to the memory and configured to direct execution of a plurality of read error recovery routines responsive to at least one uncorrectable read error in a data set retrieved from the memory, the recovery routines executed in a selected order based on an elapsed recovery time parameter for each the recovery routines and an estimated probability of success for each of the recovery routines, the processing circuit further configured to generate and store, in a local memory, a correction table which lists the plurality of read error recovery routines in the selected order, the processing circuit further configured to measure an elapsed time interval during which each of the read error recovery routines is executed and to record, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error.

19. The storage device of claim 18, further comprising a read circuit configured to, responsive to a read command, retrieve the data set from the memory and apply parity data to the retrieved data set in an attempt to detect and correct bit errors therein, wherein at least one uncorrectable error is present in the retrieved data set at a conclusion of the application of the parity data.

20. The storage device of claim 18, wherein the solid-state non-volatile memory cells are flash memory cells.