Variable data recovery scheme hierarchy
First Claim
Patent Images
1. An apparatus comprising:
- a memory comprising a plurality of solid-state non-volatile memory cells; and
a processing circuit connected to the memory and configured to direct execution of a plurality of read error recovery routines responsive to at least one uncorrectable read error in a data set retrieved from the memory, the recovery routines executed in a selected order based on an elapsed recovery time parameter for each the recovery routines and an estimated probability of success for each of the recovery routines, the processing circuit further configured to generate and store in a local memory a correction table that lists the plurality of read error recovery routines in the selected order, the processing circuit further configured to measure an elapsed time interval during which each of the read error recovery routines is executed and to record, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error.
1 Assignment
0 Petitions
Accused Products
Abstract
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory has a plurality of solid-state non-volatile memory cells. A processing circuit is connected to the memory and configured to direct the execution of a plurality of read error recovery routines in response to at least one uncorrectable read error in a data set retrieved from the memory. The recovery routines are executed in a selected order based on an elapsed recovery time parameter for each of the recovery routines and an estimated probability of success of each of the recovery routines.
-
Citations
20 Claims
-
1. An apparatus comprising:
-
a memory comprising a plurality of solid-state non-volatile memory cells; and a processing circuit connected to the memory and configured to direct execution of a plurality of read error recovery routines responsive to at least one uncorrectable read error in a data set retrieved from the memory, the recovery routines executed in a selected order based on an elapsed recovery time parameter for each the recovery routines and an estimated probability of success for each of the recovery routines, the processing circuit further configured to generate and store in a local memory a correction table that lists the plurality of read error recovery routines in the selected order, the processing circuit further configured to measure an elapsed time interval during which each of the read error recovery routines is executed and to record, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method comprising:
-
storing data to a memory comprising a plurality of solid-state non-volatile memory cells; performing a read operation to subsequently retrieve the data from the memory by applying parity data to a user data payload portion of the data to detect and correct up to a selected number of errors, wherein at a conclusion of said application of the parity data at least one uncorrectable read error remains in the retrieved data; and implementing a read error recovery routine to resolve the at least one uncorrectable read error by executing a plurality of read error recovery routines in a selected order based on an elapsed recovery time parameter to complete each of the recovery routines and an estimated probability of success of each of the recovery routines, the elapsed time recovery parameter comprising a first average time to successfully complete the associated recovery routine where a read error is successfully corrected, and a second average time to complete the associated recovery routine where said routine is unsuccessful in correcting a read error. - View Dependent Claims (13, 14, 15, 16, 17)
-
-
18. A storage device comprising:
-
a memory comprising a plurality of solid-state non-volatile memory cells; and a processing circuit connected to the memory and configured to direct execution of a plurality of read error recovery routines responsive to at least one uncorrectable read error in a data set retrieved from the memory, the recovery routines executed in a selected order based on an elapsed recovery time parameter for each the recovery routines and an estimated probability of success for each of the recovery routines, the processing circuit further configured to generate and store, in a local memory, a correction table which lists the plurality of read error recovery routines in the selected order, the processing circuit further configured to measure an elapsed time interval during which each of the read error recovery routines is executed and to record, in the local memory, an indication value indicating whether said execution was successful in correcting the at least one uncorrectable read error. - View Dependent Claims (19, 20)
-
Specification