Flash memory organization for reduced failure rate

• US 9,244,836 B2
• Filed: 11/23/2009
• Issued: 01/26/2016
• Est. Priority Date: 11/23/2009
• Status: Active Grant

• Current Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Original Assignee: AgigA Tech Incorporated (Infineon Technologies AG)
• Inventors: Sartore, Ronald H.
• Primary Examiner(s): KROFCHECK, MICHAEL C
• Application Number:
  US12/624,348
• Publication Number:
  US 20110125953A1
• Time in Patent Office: 2,255 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0646 Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory system distributes across multiple pages of a flash memory bits of a DRAM data word, the data word having a number of bits equal to a width of a row of a DRAM memory, and the bits of the data word all from a same row of the DRAM memory.

Claims

1. A memory system comprising:

a DRAM memory comprising a DRAM data word;

a flash memory comprising flash memory pages;

machine memory or circuits comprising logic to distribute across multiple of the flash memory pages different bits of the DRAM data word, the DRAM data word having a number of DRAM data word bits equal to a DRAM row width; and

machine memory or circuits comprising logic to carry out distribution of the different bits of the DRAM data word across the flash memory pages in a sequence of swatches of bits, each swatch of the sequence of swatches having a number of bits equal to a product of the DRAM row width and a page size of the flash memory, and to change a power state of one or more DRAM devices of the DRAM memory system between distribution of the each swatch of the sequence of swatches across the flash memory pages.

2. The memory system of claim 1, the DRAM data word distributed over the flash memory pages of multiple flash memory chips of the flash memory.

3. The memory system of claim 1, a number of the flash memory pages over which the DRAM data word is distributed being equal to a number of the different bits of the DRAM data word.

4. The memory system of claim 1, wherein an error correcting code (ECC) of the DRAM data word is also distributed over the flash memory pages.

5. The memory system of claim 4, a number of flash pages over which the ECC is distributed being equal to a number of data bits of the ECC.

6. The memory system of claim 1, a number of the different bits of the DRAM data word stored in each of the flash memory pages is between one and five.

7. The memory system of claim 1, further comprising:

logic to distribute the each swatch of the sequence of swatches in a sequence such that while any one particular swatch is being distributed to the flash memory pages, only a single one of the DRAM devices of the DRAM memory system is in an active power state, and the DRAM devices of the DRAM memory system that do not comprise the particular swatch remain in a low power state.

8. A method comprising:

storing in a DRAM memory a DRAM data word;

distributing across multiple flash memory pages different bits of the DRAM data word, the DRAM data word having a number of DRAM data word bits equal to a DRAM row width; and

distributing the different bits of the DRAM data word across the flash memory pages in a sequence of swatches of bits, each swatch of the sequence of swatches having a number of bits equal to a product of the DRAM row width and a page size of the flash memory, and to change a power state of one or more DRAM devices of the DRAM memory system between distribution of the each swatch of the sequence of swatches across the flash memory pages.

9. The method of claim 8, further comprising distributing the DRAM data word over the flash memory pages of multiple flash memory chips.

10. The method of claim 8, a number of the flash memory pages over which the DRAM data word is distributed being equal to a number of the different bits of the DRAM data word.

11. The method of claim 8, wherein an error correcting code (ECC) of the DRAM data word is also distributed over the flash memory pages.

12. The method of claim 11, a number of flash pages over which the ECC is distributed being equal to a number of data bits of the ECC.

13. The method of claim 8, a number of the different bits of the DRAM data word stored in each of the flash memory pages is between one and five.

14. The method of claim 8, further comprising:

distributing the each swatch of the sequence of swatches in a sequence such that while any one particular swatch is being distributed to the flash memory pages, only a single one of the DRAM devices of the DRAM memory system is in an active power state, and the DRAM devices of the DRAM memory system that do not comprise the particular swatch remain in a low power state.