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Flash memory organization for reduced failure rate

  • US 9,244,836 B2
  • Filed: 11/23/2009
  • Issued: 01/26/2016
  • Est. Priority Date: 11/23/2009
  • Status: Active Grant
First Claim
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1. A memory system comprising:

  • a DRAM memory comprising a DRAM data word;

    a flash memory comprising flash memory pages;

    machine memory or circuits comprising logic to distribute across multiple of the flash memory pages different bits of the DRAM data word, the DRAM data word having a number of DRAM data word bits equal to a DRAM row width; and

    machine memory or circuits comprising logic to carry out distribution of the different bits of the DRAM data word across the flash memory pages in a sequence of swatches of bits, each swatch of the sequence of swatches having a number of bits equal to a product of the DRAM row width and a page size of the flash memory, and to change a power state of one or more DRAM devices of the DRAM memory system between distribution of the each swatch of the sequence of swatches across the flash memory pages.

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