Merging eviction and fill buffers for cache line transactions
First Claim
Patent Images
1. A processor, comprising:
- a first cache memory; and
a bus unit comprising a plurality of buffers, the bus unit to;
allocate a selected buffer of the plurality of buffers for a fill request associated with a first cache line to be stored in the first cache memory;
load fill data responsive to the fill request from the first cache line into the selected buffer; and
transfer the fill data from the selected buffer to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer by transferring the fill data from the selected buffer to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer after one or more portions of the selected buffer have been emptied.
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Abstract
A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.
44 Citations
15 Claims
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1. A processor, comprising:
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a first cache memory; and a bus unit comprising a plurality of buffers, the bus unit to; allocate a selected buffer of the plurality of buffers for a fill request associated with a first cache line to be stored in the first cache memory; load fill data responsive to the fill request from the first cache line into the selected buffer; and transfer the fill data from the selected buffer to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer by transferring the fill data from the selected buffer to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer after one or more portions of the selected buffer have been emptied. - View Dependent Claims (2, 3, 4)
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5. A system, comprising:
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a system memory; and a processor, the processor comprising; a first cache memory; and a bus unit comprising a plurality of buffers, the bus unit to; allocate a selected buffer of the plurality of buffers for a fill request associated with a first cache line to be stored in the first cache memory; receive the first cache line and load fill data responsive to the fill request from the first cache line into the selected buffer; and transfer the fill data from the selected buffer to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer by transferring the fill data from the selected buffer to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer after one or more portions of the selected buffer have been emptied. - View Dependent Claims (6, 7, 8, 9)
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10. A method, comprising:
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allocating a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory; loading fill data responsive to the fill request from the first cache line into the selected buffer; and transferring the fill data from the selected buffer to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer by transferring the fill data from the selected buffer to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer after one or more portions of the selected buffer have been emptied. - View Dependent Claims (11, 12, 13, 14)
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15. A non-transitory computer readable storage device encoded with data that, when implemented in a manufacturing facility, adapts the manufacturing facility to create a processor, comprising:
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a first cache memory; and a bus unit comprising a plurality of buffers, the bus unit to; allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory; load fill data responsive to the fill request from the first cache line into the selected buffer; and transfer the fill data from the selected buffer to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer by transferring the fill data from the selected buffer to the first cache memory to empty the selected buffer and transferring the eviction data into the emptied selected buffer after one or more portions of the selected buffer have been emptied.
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Specification