Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses

• US 9,244,846 B2
• Filed: 07/06/2012
• Issued: 01/26/2016
• Est. Priority Date: 07/06/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Frey, Bradly G., May, Cathy, Williams, Derek E.
• Primary Examiner(s): Li, Aimee
• Assistant Examiner(s): Tsang, Kenneth
• Application Number:
  US13/543,325
• Publication Number:
  US 20140013060A1
• Time in Patent Office: 1,299 Days
• Field of Search: 711/141
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 9/466 Transaction processing

Abstract

A data processing system implements a weak consistency memory model for a distributed shared memory system. The data processing system concurrently executes, on a plurality of processor cores, one or more transactional memory instructions within a memory transaction and one or more non-transactional memory instructions. The one or more non-transactional memory instructions include a non-transactional store instruction. The data processing system commits the memory transaction to the distributed shared memory system only in response to enforcement of causality of the non-transactional store instruction with respect to the memory transaction.

Claims

1. A method of data processing, comprising:

in a data processing system implementing memory transactions and a weak consistency memory model for a distributed shared memory system, concurrently executing on a plurality of processor cores one or more transactional memory instructions within a pending memory transaction and one or more non-transactional memory instructions including a non-transactional store instruction, wherein the plurality of processor cores includes at least three processor cores;

committing the pending memory transaction to the distributed shared memory system of the data processing system only in response to both;

all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction completing atomically without a conflict with any memory access of any other thread; and

enforcement of causality of the non-transactional store instruction with respect to the pending memory transaction by ensuring visibility to all of the plurality of processor cores of a value stored to the distributed shared memory system by the non-transactional store instruction and read by a transactional load instruction within the pending memory transaction.

2. The method of claim 1, wherein:

the data processing system includes a system fabric that distributes memory access requests to the shared distributed memory system;

the method further includes snooping, on the system fabric, a store request corresponding to the non-transactional store instruction and snooping, on the system fabric, a read request corresponding to the transactional load instruction; and

the committing includes;

in response to snooping the read request while the store request is pending, preventing the memory transaction from committing until the store request is no longer pending.

3. The method of claim 2, wherein preventing the memory transaction from committing includes providing a retry response to a request on the system fabric to commit the memory transaction.

4. The method of claim 1, wherein the committing further includes committing the memory transaction only in response to an invalidation necessitated by a memory update of a transactional store instruction among the one or more transactional memory instructions in the memory transaction having fully propagated throughout the distributed shared memory system.

5. The method of claim 1, and further comprising:

in response to detecting a conflict for the memory transaction, refraining from committing the transaction to the distributed shared memory system.

6. The method of claim 5, and further comprising:

in response to detecting a conflict for the memory transaction, refraining from executing one or more instructions in the memory transaction and invoking execution of a fail handler.

7. The method of claim 1, and further comprising controlling commitment of the memory transaction by one or more lower level store-in cache memories in the distributed shared memory system.

8. A data processing system, comprising:

a plurality of processor cores including at least three processor cores, wherein the plurality of processor cores concurrently executes one or more transactional memory instructions within a pending memory transaction and one or more non-transactional memory instructions including a non-transactional store instruction; and

a distributed shared memory system that is coupled to the plurality of processor cores, that implements a weak consistency memory model, and that supports memory transactions, wherein following execution of all of the one or more transactional memory instructions in the pending memory transaction;

the distributed shared memory system refrains from committing the pending memory transaction to the distributed shared memory system in response to all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction failing to complete atomically without a conflict with any memory access of any other thread;

the distributed shared memory system commits the pending memory transaction to the distributed shared memory system only in response to both;

all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction completing atomically without a conflict with any memory access of any other thread; and

enforcement of causality of the non-transactional store instruction with respect to the pending memory transaction by ensuring visibility to all of the plurality of processor cores of a value stored to the distributed shared memory system by the non-transactional store instruction and read by a transactional load instruction within the pending memory transaction.

9. The data processing system of claim 8, wherein:

the data processing system includes a system fabric that distributes memory access requests to the shared distributed memory system;

the distributed shared memory system includes;

a snoop machine that snoops, on the system fabric, a store request corresponding to the non-transactional store instruction and snoops, on the system fabric, a read request corresponding to the transactional load instruction; and

causality resolution logic that, responsive to the read request being snooped while the store request is pending, prevents the memory transaction from committing until the store request is no longer pending.

10. The data processing system of claim 9, wherein the causality resolution logic prevents the memory transaction from committing by causing a retry response to be provided to a request on the system fabric to commit the memory transaction.

11. The data processing system of claim 8, wherein the distributed shared memory system commits the memory transaction only in response to an invalidation necessitated by a memory update of a transactional store instruction among the one or more transactional memory instructions in the memory transaction having fully propagated throughout the distributed shared memory system.

12. The data processing system of claim 8, wherein the distributed shared memory system, responsive to detecting a conflict for the memory transaction, refrains from committing the transaction to the distributed shared memory system.

13. The data processing system of claim 12, wherein a processor core among the plurality of processor cores that executes the memory transaction, responsive to detecting a conflict for the memory transaction during execution of the memory transaction, refrains from executing one or more instructions in the memory transaction and invokes execution of a fail handler.

14. The data processing system of claim 8, wherein the distributed shared memory system includes one or more lower level store-in cache memories that control commitment of the memory transaction.

23. The data processing system of claim 8, wherein the distributed shared memory system enforces causality of the non-transactional store instruction with respect to the memory transaction by ensuring that the one or more transactional memory instructions within the memory transaction cannot read the effects of a computation caused by the non-transactional store instruction before the memory update can be read by one or more transactional memory instructions in the memory transaction.

15. A processing unit for a multiprocessor data processing system including

a plurality of processor cores including at least three processor cores, the processing unit comprising:

a processor core that executes a pending memory transaction including one or more transactional memory access instructions; and

a multilevel cache hierarchy coupled to the processor core and configured to form a portion of a distributed shared memory system implementing a weak consistency memory model and memory transactions in the multiprocessor data processing system,

wherein following execution of all of the one or more transactional memory instructions in the pending memory transaction;

the cache hierarchy does not permit the pending memory transaction to commit to the distributed shared memory system in response to all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction failing to complete atomically without a conflict with any memory access of any other thread;

the cache hierarchy permits the pending memory transaction to commit to the distributed shared memory system only in response to both;

all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction completing atomically without a conflict with any memory access of any other thread; and

enforcement of causality of the non-transactional store instruction with respect to the pending memory transaction by ensuring visibility to all of the plurality of processor cores of a value stored to the distributed shared memory system by the non-transactional store instruction and read by a transactional load instruction within the pending memory transaction.

16. The processing unit of claim 15, wherein:

the data processing system includes a system fabric that distributes memory access requests to the shared distributed memory system;

the cache hierarchy includes;

a snoop machine that snoops, on the system fabric, a store request corresponding to the non-transactional store instruction and snoops, on the system fabric, a read request corresponding to the transactional load instruction; and

causality resolution logic that, responsive to the read request being snooped while the store request is pending, prevents the memory transaction from committing until the store request is no longer pending.

17. The processing unit of claim 16, wherein the causality resolution logic prevents the memory transaction from committing by causing a retry response to be provided to a request on the system fabric to commit the memory transaction.

18. The processing unit of claim 15, wherein the cache hierarchy commits the memory transaction only in response to an invalidation necessitated by a memory update of a transactional store instruction among the one or more transactional memory instructions in the memory transaction having fully propagated throughout the distributed shared memory system.

19. The processing unit of claim 15, wherein the cache hierarchy, responsive to detecting a conflict for the memory transaction, refrains from committing the transaction to the distributed shared memory system.

20. The processing unit of claim 19, wherein a processor core, responsive to detecting a conflict for the memory transaction during execution of the memory transaction, refrains from executing one or more instructions in the memory transaction and invokes execution of a fail handler.

24. The processing unit of claim 15, wherein the distributed shared memory system enforces causality of the non-transactional store instruction with respect to the memory transaction by ensuring that the one or more transactional memory instructions within the memory transaction cannot read the effects of a computation caused by the non-transactional store instruction before the memory update can be read by one or more transactional memory instructions in the memory transaction.

21. A design structure tangibly embodied in a machine-readable memory for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

a processing unit for a multiprocessor data processing system including a plurality of processor cores including at least three processor cores, the processing unit including;

a processor core that executes a pending memory transaction including one or more transactional memory access instructions; and

a multilevel cache hierarchy coupled to the processor core and configured to form a portion of a distributed shared memory system implementing a weak consistency memory model and memory transactions in the multiprocessor data processing system, wherein following execution of all of the one or more transactional memory instructions in the pending memory transaction;

the cache hierarchy does not permit the pending memory transaction to commit to the distributed shared memory system in response to all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction failing to complete atomically without a conflict with any memory access of any other thread;

the cache hierarchy permits the pending memory transaction to commit to the distributed shared memory system only in response to both;

all accesses to the distributed shared memory system caused by constituent memory instructions of the pending memory transaction completing atomically without a conflict with any memory access of any other thread; and

enforcement of causality of the non-transactional store instruction with respect to the pending memory transaction by ensuring visibility to all of the plurality of processor cores of a value stored to the distributed shared memory system by the non-transactional store instruction and read by a transactional load instruction within the pending memory transaction.

22. The design structure of claim 21 wherein the design structure comprises a hardware description language (HDL) design structure.

25. The design structure of claim 21, wherein the distributed shared memory system enforces causality of the non-transactional store instruction with respect to the memory transaction by ensuring that the one or more transactional memory instructions within the memory transaction cannot read the effects of a computation caused by the non-transactional store instruction before the memory update can be read by one or more transactional memory instructions in the memory transaction.