Method, system, and apparatus for page sizing extension
First Claim
Patent Images
1. A method to support a plurality of page sizes of a virtual demand-paged memory system without significantly increasing miss-handling penalties, the method comprising:
- initializing a fixed plurality of page table entries for a fixed plurality of pages contiguous in a memory, each page having a first page size, wherein a linear address for each page in each page table entry corresponds to a physical address and the fixed plurality of pages is aligned;
setting a first bit in each of the fixed plurality of page table entries, for access by an operation during a highest level of a page table walk on a multiple level page table hierarchy, to a value indicating whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size; and
when a miss occurs for at least one of the fixed plurality of pages, performing said page table walk.
2 Assignments
0 Petitions
Accused Products
Abstract
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
-
Citations
20 Claims
-
1. A method to support a plurality of page sizes of a virtual demand-paged memory system without significantly increasing miss-handling penalties, the method comprising:
-
initializing a fixed plurality of page table entries for a fixed plurality of pages contiguous in a memory, each page having a first page size, wherein a linear address for each page in each page table entry corresponds to a physical address and the fixed plurality of pages is aligned; setting a first bit in each of the fixed plurality of page table entries, for access by an operation during a highest level of a page table walk on a multiple level page table hierarchy, to a value indicating whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size; and when a miss occurs for at least one of the fixed plurality of pages, performing said page table walk. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. An apparatus comprising a processor:
-
to access a memory via a paging system having a first page size and one or more page tables; to initialize a fixed plurality of page table entries for a fixed plurality of contiguous pages, wherein each page has the first page size and a linear address for each page in each page table entry corresponds to a physical address and the fixed plurality of pages is aligned; to set a first bit in each of the fixed plurality of page table entries, for access by an operation during a highest level of a page table walk on a multiple level page table hierarchy, the first bit indicating whether or not the fixed plurality of contiguous pages is to be treated as one combined page having a second page size larger than the first page size; and when a miss occurs for a first one of the fixed plurality of contiguous pages, to perform said page table walk. - View Dependent Claims (10, 11, 12, 13, 14)
-
-
15. A system comprising:
-
a bus; a memory coupled to the bus and accessible by a paging system having a first page size and one or more page tables; a processor coupled to the bus to create a second page having a second size, the second size larger than the first size, from a plurality of first pages contiguous and having the first size, the processor to initialize a plurality of page table entries for the plurality of first pages, wherein each of the first pages has a linear address corresponding to a physical address and the plurality of first pages is aligned, and the processor to set a first bit in each of the plurality of page table entries, for access by an operation during a highest level of a page table walk on a multiple level page table hierarchy, indicating whether or not the plurality of first pages is to be treated as the second page; and when a miss occurs for the second page, to perform said page table walk. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification