Semiconductor device having Schmitt trigger NAND circuit and Schmitt trigger inverter

• US 9,245,589 B2
• Filed: 03/18/2014
• Issued: 01/26/2016
• Est. Priority Date: 03/25/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Aoki, Takeshi, Kurokawa, Yoshiyuki, Kozuma, Munehiro
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US14/217,793
• Publication Number:
  US 20140286076A1
• Time in Patent Office: 679 Days
• Field of Search: 365/72, 365/189.05, 365/205, 365/230.08
• US Class Current: 1/1
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load

Abstract

A nonvolatile semiconductor device which can be driven at low voltage is provided. A nonvolatile semiconductor device with low power consumption is provided. A Schmitt trigger NAND circuit and a Schmitt trigger inverter are included. Data is held in a period when the supply of power supply voltage is continued, and a potential corresponding to the data is stored at a node electrically connected to a capacitor before a period when the supply of power supply voltage is stopped. By utilizing a change in channel resistance of a transistor whose gate is connected to the node, the data is restored in response to the restart of the supply of power supply voltage.

Claims

1. A semiconductor device comprising:

a memory circuit portion;

a Schmitt trigger inverter;

a first transistor;

a second transistor;

a third transistor; and

a capacitor,

wherein an input terminal of the Schmitt trigger inverter and one of a source and a drain of the first transistor are electrically connected to the memory circuit portion,

wherein an output terminal of the Schmitt trigger inverter is electrically connected to one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the second transistor, a first electrode of the capacitor, and a gate of the third transistor are electrically connected to one another,

wherein a second electrode of the capacitor and one of a source and a drain of the third transistor are electrically connected to a wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source and the drain of the first transistor.

2. The semiconductor device according to claim 1,

wherein the memory circuit portion comprises a latch circuit, and

wherein the latch circuit comprises a Schmitt trigger NAND circuit.

3. The semiconductor device according to claim 1,

wherein the memory circuit portion comprises a flip-flop circuit, and

wherein the flip-flop circuit comprises a Schmitt trigger NAND circuit.

4. The semiconductor device according to claim 1, wherein the second transistor comprises an oxide semiconductor.

5. The semiconductor device according to claim 4, wherein each of the first transistor and the third transistor comprises a semiconductor material other than the oxide semiconductor.

6. A semiconductor device comprising:

a latch circuit comprising a first node and a second node; and

a circuit comprising a first block and a second block,

wherein each of the first block and the second block comprises;

a Schmitt trigger inverter;

a first transistor;

a second transistor;

a third transistor;

a capacitor; and

a third node where one of a source and a drain of the second transistor, a first electrode of the capacitor, and a gate of the third transistor are electrically connected to one another,

wherein an output terminal of the Schmitt trigger inverter is electrically connected to the other of the source and the drain of the second transistor,

wherein a second electrode of the capacitor and one of a source and a drain of the third transistor are electrically connected to a first wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the first transistor,

wherein an input terminal of the Schmitt trigger inverter and the other of the source and the drain of the first transistor in the first block are electrically connected to the first node, and

wherein an input terminal of the Schmitt trigger inverter and the other of the source and the drain of the first transistor in the second block are electrically connected to the second node.

7. The semiconductor device according to claim 6, further comprising:

a second wiring electrically connected to a gate of the first transistor in each of the first block and the second block, and

a third wiring electrically connected to a gate of the third transistor in each of the first block and the second block.

8. The semiconductor device according to claim 6,

wherein the latch circuit is configured to hold one of a first potential and a second potential at the first node and the other of the first potential and the second potential at the second node in a period when a supply of a power supply voltage is continued, and

wherein the circuit is configured to hold the other of the first potential and the second potential at the third node in the first block and the one of the first potential and the second potential at the third node in the second block in a period when the supply of the power supply voltage is stopped.

9. The semiconductor device according to claim 6, wherein the latch circuit comprises a Schmitt trigger NAND circuit.

10. The semiconductor device according to claim 6, wherein the second transistor comprises an oxide semiconductor.

11. The semiconductor device according to claim 10, wherein each of the first transistor and the third transistor comprises a semiconductor material other than the oxide semiconductor.

12. A semiconductor device comprising:

a flip-flop circuit comprising a first node and a second node; and

a circuit comprising a first block and a second block,

wherein each of the first block and the second block comprises;

a Schmitt trigger inverter;

a first transistor;

a second transistor;

a third transistor;

a capacitor; and

a third node where one of a source and a drain of the second transistor, a first electrode of the capacitor, and a gate of the third transistor are electrically connected to one another,

wherein an output terminal of the Schmitt trigger inverter is electrically connected to the other of the source and the drain of the second transistor,

wherein a second electrode of the capacitor and one of a source and a drain of the third transistor are electrically connected to a first wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the first transistor,

wherein an input terminal of the Schmitt trigger inverter and the other of the source and the drain of the first transistor in the first block are electrically connected to the first node, and

wherein an input terminal of the Schmitt trigger inverter and the other of the source and the drain of the first transistor in the second block are electrically connected to the second node.

13. The semiconductor device according to claim 12, further comprising:

a second wiring electrically connected to a gate of the first transistor in each of the first block and the second block, and

a third wiring electrically connected to a gate of the third transistor in each of the first block and the second block.

14. The semiconductor device according to claim 12,

wherein the flip-flop circuit is configured to hold one of a first potential and a second potential at the first node and the other of the first potential and the second potential at the second node in a period when a supply of a power supply voltage is continued, and

wherein the circuit is configured to hold the other of the first potential and the second potential at the third node in the first block and the one of the first potential and the second potential at the third node in the second block in a period when the supply of the power supply voltage is stopped.

15. The semiconductor device according to claim 12, wherein the flip-flop circuit comprises a Schmitt trigger NAND circuit.

16. The semiconductor device according to claim 15, wherein the flip-flop circuit further comprises a Schmitt trigger AND circuit.

17. The semiconductor device according to claim 12, wherein the second transistor comprises an oxide semiconductor.

18. The semiconductor device according to claim 17, wherein each of the first transistor and the third transistor comprises a semiconductor material other than the oxide semiconductor.