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Memory device including a SRAM memory plane and a non volatile memory plane, and operating methods

  • US 9,245,624 B2
  • Filed: 06/06/2014
  • Issued: 01/26/2016
  • Est. Priority Date: 06/12/2013
  • Status: Active Grant
First Claim
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1. A memory device comprising:

  • an SRAM-type elementary memory cell having first and second inverter coupled to one another crosswise;

    a first non-volatile memory unit having a first non-volatile elementary memory cell with a first floating-gate transistor, the first floating-gate transistor havinga first conduction electrode directly connected to a supply terminal,a control electrode coupled to a first control line, anda second conduction electrode;

    a second non-volatile memory unit having a second non-volatile elementary memory cell with a second floating-gate transistor, the second floating-gate transistor havinga first conduction electrode directly connected to the supply terminal,a control electrode coupled to the first control line, anda second conduction electrode;

    a controllable interconnection stage with a first portion coupled between the second conduction electrode of the first floating-gate transistor and an output of the first inverter and a second portion coupled between the second conduction electrode of the second floating-gate transistor and an output of the second inverter; and

    a control circuit configured to cause the first and second floating-gate transistors to turn off when a data item stored in the SRAM-type elementary memory cell is differentially programmed into the first and second non-volatile memory units.

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