Memory device including a SRAM memory plane and a non volatile memory plane, and operating methods

• US 9,245,624 B2
• Filed: 06/06/2014
• Issued: 01/26/2016
• Est. Priority Date: 06/12/2013
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: Stmicroelectronics Rousset SAS (STMicroelectronics NV)
• Inventors: Tailliet, Franois, Battista, Marc
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/298,264
• Publication Number:
  US 20140369120A1
• Time in Patent Office: 599 Days
• Field of Search: 365/185.08
• US Class Current: 1/1
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Claims

1. A memory device comprising:

an SRAM-type elementary memory cell having first and second inverter coupled to one another crosswise;

a first non-volatile memory unit having a first non-volatile elementary memory cell with a first floating-gate transistor, the first floating-gate transistor having

a first conduction electrode directly connected to a supply terminal,

a control electrode coupled to a first control line, and

a second conduction electrode;

a second non-volatile memory unit having a second non-volatile elementary memory cell with a second floating-gate transistor, the second floating-gate transistor having

a first conduction electrode directly connected to the supply terminal,

a control electrode coupled to the first control line, and

a second conduction electrode;

a controllable interconnection stage with a first portion coupled between the second conduction electrode of the first floating-gate transistor and an output of the first inverter and a second portion coupled between the second conduction electrode of the second floating-gate transistor and an output of the second inverter; and

a control circuit configured to cause the first and second floating-gate transistors to turn off when a data item stored in the SRAM-type elementary memory cell is differentially programmed into the first and second non-volatile memory units.

2. The device according to claim 1, further comprising a first negative control voltage terminal that is coupled to the first control line during the differential programming.

3. The device according to claim 1, wherein the first and second floating-gate transistors and the interconnection stage are coupled so as to selectively confer a written state on the first non-volatile elementary memory cell and an erased state on the second non-volatile elementary memory cell, after completion of the differential programming.

4. The device according to claim 3, wherein the output of the first inverter is in a high logic state and the output of the second inverter is in a low logic state based on a logic value of the data item stored in the SRAM-type elementary cell.

5. The device according to claim 3, wherein, during an operation of reloading a data item programmed differentially in the two first and second non-volatile elementary memory units into the SRAM-type elementary memory cell, the first and second floating-gate transistors are configured so that the first floating-gate transistor is on and the second floating-gate transistor is off.

6. The device according to claim 1, wherein the interconnection stage comprises:

a second control line;

a third control line;

a first interconnection transistor with a current path coupled between the second conduction electrode of the first floating-gate transistor and the output of the first inverter and a control electrode coupled to the second control line;

a second interconnection transistor with a current path coupled between the second conduction electrode of the second floating-gate transistors and the output of the second inverter and a control electrode coupled to the second control line;

a third interconnection transistor with a current path coupled between the second conduction electrode the first floating-gate transistor and an input of the first inverter and a control electrode coupled to the third control line; and

a fourth interconnection transistor with a current path coupled between the second conduction electrode the second floating-gate transistor and an input of the second inverter and a control electrode coupled to the third control line.

7. The device according to claim 6, wherein, during the differential programming, the second control line coupled to receive a second control voltage turning on the first and second interconnection transistors and the third control line is coupled to receive a third control voltage turning off the third and fourth interconnection transistors and, during a reloading operation, the second control line is coupled to receive a second control voltage turning off the first and second interconnection transistors and the third control line is coupled to receive a third control voltage turning on the third and fourth interconnection transistors.

8. The device according to claim 1, wherein the supply terminal is held at a ground potential during operation.

9. The device according to claim 1, wherein each non-volatile elementary memory cell is a cell of EEPROM type.

10. The device according to claim 1, wherein the memory device includes a plurality of memory cells, each memory cell comprising:

an SRAM-type elementary memory cell having first and second inverter coupled to one another crosswise;

a first non-volatile memory unit having a first non-volatile elementary memory cell with a first floating-gate transistor, the first floating-gate transistor having a first conduction electrode coupled to a supply terminal, a control electrode coupled to a first control line, and a second conduction electrode; and

a second non-volatile memory unit having a second non-volatile elementary memory cell with a second floating-gate transistor, the second floating-gate transistor having a first conduction electrode coupled to the supply terminal, a control electrode coupled to the first control line, and a second conduction electrode; and

a controllable interconnection stage with a first portion coupled between the second conduction electrode of the first floating-gate transistor and an output of the first inverter and a second portion coupled between the second conduction electrode of the second floating-gate transistor and an output of the second inverter.

11. The device according to claim 10, comprising a memory map containing the plurality of memory cells, which are organized into blocks of cells, the device further comprising control circuitry configured to operate in

a first state, in which the control circuitry is capable of putting all memory cells of the memory map either into a read or write mode of SRAM type or into a write mode for the groups of non-volatile elementary memory cells;

and

a second state, in which the control circuitry is capable of selectively putting, on a block-by-block basis, all memory cells of a block either into a read or write mode of SRAM type or into a write mode of the groups of non-volatile elementary memory cells.

12. The device according to claim 11, further comprising a receiver configured to receive successive blocks of data and management circuitry configured to put the control circuitry into the second state;

store a current block of data in the SRAM-type elementary memory cells of the memory cells of a block of memory cells;

then carry out a non-volatile write cycle for writing the data thus written to the SRAM-type elementary cells to the non-volatile elementary memory cells of the memory cells of the block of cells; and

at the same time as the non-volatile write cycle, store the next block of data in the SRAM-type elementary memory cells of the memory cells of another block of memory cells.

13. The device according to claim 11, wherein the memory map contains the plurality of memory cells organized into two rows and columns, and each block of memory cells has several rows of memory cells.

14. The device according to claim 1, wherein each non-volatile elementary memory cell further comprises an isolation stage having a fourth control line and an isolation transistor coupled between the first conduction electrode of the respective floating-gate transistor and the supply terminal, the control electrodes of all isolation transistors being coupled to the fourth control line.

15. The device according to claim 14, comprising a memory map containing the plurality of memory cells and control circuitry configured so as, when power is supplied to the device, not to supply power to the memory map and to authorize a supply of power to a set of at least one memory cell and reloading the SRAM-type elementary memory cell of the at least one memory cell with a content of the non-volatile elementary memory cells, only during addressing of the SRAM-type elementary memory cell.

16. The device according to claim 15, wherein the set has more than one memory cell and the control circuitry is configured so as, during the supply of power to the device, not to supply power to the memory map and to authorize the supply of power to the set of memory cells and reloading of all the SRAM-type elementary memory cells of the set of memory cells with a content of the corresponding non-volatile elementary memory cells, only during the addressing of at least one SRAM-type elementary memory cell of the set.

17. The device according to claim 16, wherein the memory map contains the plurality of memory cells organized into rows and columns, and the set of memory cells has at least one row of memory cells.

18. A memory device, comprising:

a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise; and

two groups, each group having at least two parallel-coupled non-volatile elementary memory cells, the non-volatile elementary memory cells of the two groups being coupled firstly to a supply terminal and secondly to outputs and to inputs of the two inverters via a controllable interconnection stage, wherein each non-volatile elementary memory cell includes a floating-gate transistor, each floating-gate transistor of each non-volatile elementary memory cell including

a first conduction electrode directly connected to the supply terminal,

a second conduction electrode, and

a control electrode coupled to a first control line.

19. The device according to claim 18, wherein the controllable interconnection stage comprises

a second control line;

a third control line;

two first interconnection transistors respectively coupled between second conduction electrodes of the floating-gate transistors of the non-volatile elementary memory cells of the two groups and outputs of the two inverters of the SRAM-type elementary memory cell, and having a control electrode coupled to the second control line; and

two second interconnection transistors respectively coupled between the second conduction electrodes of the floating-gate transistors of the non-volatile elementary memory cells of the two groups and inputs of the two inverters of the SRAM-type elementary memory cell, and having a control electrode coupled to the third control line.

20. The device according to claim 19, wherein each group comprises a pair of non-volatile elementary memory cells coupled in parallel and wherein the controllable interconnection stage further comprises two first transistors having shorted conduction electrodes respectively coupled in series with the two first interconnection transistors and each having a control electrode coupled to the third control line, and two second transistors having shorted conduction electrodes respectively coupled in series with the two second interconnection transistors and each having a control electrode coupled to the second control line.

21. The device according to claim 18, comprising a memory map containing a plurality memory cells organized into rows and columns, bit lines and complementary bit lines common to the memory cells of at least some pairs of adjacent columns of cells, two different word lines associated with each row of cells, access transistors of the SRAM-type elementary cells of the memory cells being respectively coupled to the corresponding common bit lines and complementary bit lines, and control electrodes of the two pairs of access transistors of two adjacent cells of SRAM type are respectively coupled to the two different word lines.

22. A method of operating a memory device that comprises:

a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise;

two groups, each group having a non-volatile elementary memory cell, the non-volatile elementary memory cells of the two groups being coupled firstly to a supply terminal and secondly to outputs and to inputs of the two inverters via a controllable interconnection stage, wherein each non-volatile elementary memory cell includes a floating-gate transistor, all floating-gate transistors having a first conduction electrode coupled to the supply terminal and a control electrode coupled to a first control line;

wherein the controllable interconnection stage comprises

a second control line;

a third control line;

two first interconnection transistors respectively coupled between second conduction electrodes of the floating-gate transistors of the non-volatile elementary memory cells of the two groups and outputs of the two inverters of the SRAM-type elementary memory cell, and having a control electrode coupled to the second control line; and

two second interconnection transistors respectively coupled between the second conduction electrodes of the floating-gate transistors of the non-volatile elementary memory cells of the two groups and inputs of the two inverters of the SRAM-type elementary memory cell, and having a control electrode coupled to the third control line;

wherein the method comprises writing a data item stored in the SRAM-type elementary memory cell to the two groups of non-volatile elementary memory cells of the memory cell, the method comprising an erase cycle for the groups of non-volatile elementary memory cells followed by a differential programming cycle;

wherein the erase cycle comprises;

turning on the first interconnection transistors by applying a control voltage to the second control line;

turning off the second interconnection transistors by applying a control voltage to the third control line; and

wherein the differential programming cycle comprises;

turning off the floating-gate transistor for each non-volatile elementary memory cell by applying a programming voltage to the first control line, wherein the floating-gate transistor for each non-volatile elementary memory cell is turned off during an entirety of the differential programming cycle; and

then

stopping application of the programming voltage to the first control line so as to put the at least one non-volatile elementary memory cell of one of the groups into a written state and the at least one non-volatile elementary memory cell of the other group into an erased state.

23. The method according to claim 22, wherein at least one of the programming voltages comprises a negative programming voltage.

24. The method of claim 22, further comprising reloading into the SRAM-type elementary memory cell of the memory cell a data item programmed by the differential programming cycle, the reloading comprising:

turning off the first interconnection transistors;

turning on the second interconnection transistors; and

turning on the floating-gate transistor of the at least one non-volatile elementary memory cell in the written state and turning off the floating-gate transistor of the at least one non-volatile elementary memory cell in the erased state.

25. The method according to claim 22, wherein the memory cell further comprises an isolation stage having a fourth control line and isolation transistors respectively coupled between the first conduction electrode of each floating-gate transistor and the supply terminal, control electrodes of all isolation transistors being coupled to the fourth control line, wherein the erase cycle comprises:

turning on the first interconnection transistors;

turning off the second interconnection transistors;

turning off the isolation transistors; and

turning on the floating-gate transistors by applying an erase voltage to the first control line.

26. The method of claim 25, further comprising reloading into the SRAM-type elementary memory cell a data item programmed by the differential programming cycle, the reloading comprising:

turning off the first interconnection transistors;

turning on the second interconnection transistors;

turning on the isolation transistors; and

turning on the floating-gate transistor of the at least one non-volatile elementary memory cell in the written state and turning off the floating-gate transistor of the at least one non-volatile elementary memory cell in the erased state.