Method for non-volatile memory having 3D array of read/write elements with efficient decoding of vertical bit lines and word lines

• US 9,245,629 B2
• Filed: 10/18/2013
• Issued: 01/26/2016
• Est. Priority Date: 06/08/2010
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Samachisa, George, Fasoli, Luca, Higashitani, Masaaki, Scheuerlein, Roy Edwin
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Chen, Xiaochun L
• Application Number:
  US14/057,971
• Publication Number:
  US 20140043911A1
• Time in Patent Office: 830 Days
• Field of Search: 365/185.18
• US Class Current: 1/1
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/845 the switching components being connected to a common vertical conductor
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/245 the species being metal cations, e.g. programmable metallization cells
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx
• CPC Class Codes: H10N 70/8845 Carbon or carbides

Abstract

A three-dimensional array of memory elements is formed across multiple layers of planes positioned at different distances above a semiconductor substrate. The memory elements reversibly change a level of electrical conductance in response to a voltage difference being applied across them. The three-dimensional array includes a two-dimensional array of pillar lines from the substrate through the multiple layers of planes. A first set of pillar lines acts as local bit lines for accessing the memory elements together with an array of word lines on each plane. A second set of pillar lines is connected to the word lines. An array of metal lines on the substrate is switchable connected to the pillar lines to provide access to the first and second sets of pillar lines, thereby to provide access respectively to the bit lines and word lines of the three-dimensional array.

Claims

1. A method of operating a re-programmable non-volatile memory system, comprising:

utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having x, y and z-directions and which comprises;

a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate;

a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction, wherein said plurality of first conductive lines is partitioned into a first set of first conductive lines acting as local bit lines and into a second set of first conductive lines;

a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of first conductive lines in the individual planes, wherein said plurality of second conductive lines act as word lines and the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes;

a plurality of non-volatile re-programmable memory elements individually connected between the first set of first conductive lines and second conductive lines adjacent the crossings thereof at a first set of the plurality of locations;

a plurality of connectors individually connected between the second set of first conductive lines and second conductive lines adjacent the crossings thereof at a second set of the plurality of locations;

a plurality of third conductive lines partitioned into first and second groups of third conductive lines; and

a first group of select devices arranged to switch a selected row of first conductive lines in the x-direction to the first set of third conductive lines; and

a second group of select devices arranged to switch a selected set of the plurality of second conductive lines to respective second set of third conductive lines; and

wherein the select devices each has a source terminal and a drain terminal that are aligned with the two-dimensional array of first conductive lines in the x-y plane; and

wherein the source and drain terminals of each select device are aligned diagonally in the x-y plane;

selecting one or more of the plurality of memory elements by applying select control signals to the first and second groups of select devices in order to connect selected row of the first set of first conductive lines to individual ones of the first set of third conductive lines and to connect selected second conductive lines, via the second set of first conductive lines, to individual ones of the second set of third conductive lines; and

causing the selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying either a first or a second electrical stimulus through the individual ones of the first and second sets of third conductive lines between which the selected one or more of the plurality of memory elements are operably connected.

2. The method as in claim 1, wherein:

each adjacent pair of the second conductive lines are disposed around a corresponding row of first conductive lines in the x-direction for operating exclusively therewith.

3. The method as in claim 1, wherein the selected set of the plurality of second conductive lines includes adjacent pairs of the second conductive lines that are disposed around the selected row of first conductive lines at all of the plurality of planes.

4. The method as in claim 1, wherein

the third conductive lines are elongated in the y-direction,

the select devices are arranged to make those of the first conductive lines aligned in the x-direction connectable with selected ones of the plurality of third conductive lines, and

a plurality of control lines extending in the x-direction and individually connected with a plurality of the select devices aligned in the x-direction to enable connection of a plurality of first conductive lines aligned in the x-direction with different ones of the third conductive lines.

5. The method as in claim 1, wherein a row of first conductive lines are simultaneously switched by two rows of adjacent select devices to connect to different ones of the third conductive lines.

6. The method as in claim 1, wherein the plurality of select devices and the plurality of third conductive lines are formed in a semiconductor substrate and the plurality of planes are formed as a stack over the semiconductor substrate.

7. The method as in claim 6, wherein a row of first conductive lines are simultaneously switched by two rows of adjacent select devices to connect to different ones of the third conductive lines.

8. The method as in claim 6, wherein a row of first conductive lines are simultaneously switched by two rows of adjacent select devices to connect to different ones of the third conductive lines.

9. The method as in claim 1, wherein:

the plurality of select devices are formed in a semiconductor substrate;

the plurality of planes are formed as a stack over the semiconductor substrate; and

the plurality of third conductive lines are formed over the stack.

10. The method as in claim 9, further comprising:

vertical interconnecting conductive lines through the stack between individual select devices and respective third conductive lines.

11. The method as in claim 1, wherein the individual memory elements are characterized by including a material that reversibly changes its level of electrical conductance between at least first and second stable levels in response to an electrical stimulus being applied through the first and second conductive lines between which the memory element is connected.

12. The method as in claim 1, wherein the plurality of non-volatile re-programmable memory elements are constituted from a chalcogenide.

13. The method as in claim 1, wherein the plurality of non-volatile re-programmable memory elements are constituted from a phase change material.

14. The method as in claim 1, wherein the plurality of nonvolatile re-programmable memory elements are constituted from a metal oxide.

15. The method as in claim 1, wherein the plurality of first conductive lines is formed from P+ doped polysilicon.

16. The method as in claim 1, wherein the plurality of second conductive lines is formed from metal.

17. The method as in claim 1, wherein the plurality of third conductive lines is formed from metal.