Method of operating a split gate flash memory cell with coupling gate

• US 9,245,638 B2
• Filed: 03/17/2014
• Issued: 01/26/2016
• Est. Priority Date: 05/13/2011
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Do, Nhan, Cuevas, Elizabeth A., Tkachev, Yuri, Tadayoni, Mandana, Om'mani, Henry A.
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US14/216,776
• Publication Number:
  US 20140198578A1
• Time in Patent Office: 680 Days
• Field of Search: 365/185.14
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the fir region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

Claims

1. A method of reading a memory cell that comprises a substrate of a first conductivity type, first and second regions spaced apart in the substrate of a second conductivity type which define a channel region in the substrate therebetween, a floating gate disposed over and insulated from a first portion of the channel region and the first region, a control gate having first and second portions, wherein the control gate first portion is disposed over and insulated from a second portion of the channel region and is disposed laterally adjacent to and insulated from the floating gate, wherein the control gate second portion is disposed over and insulated from the floating gate, and a coupling gate disposed over and insulated from the first region and laterally adjacent to and insulated from the floating gate, wherein the coupling gate includes a first portion that is disposed over and insulated from the first region and laterally adjacent to and insulated from the floating gate, and a second portion that is disposed over and insulated from the floating gate, with no portion of the coupling gate being disposed over or under the control gate, the method comprising:

applying a positive voltage to the control gate;

applying a positive voltage to the coupling gate; and

applying a positive voltage to one of the first and second regions.

2. The method of claim 1, wherein the positive voltage applied to the control gate is equal to the positive voltage applied to the coupling gate.

3. The method of claim 1, further comprising:

applying a ground voltage to the other one of the first and second regions.