Thin film transistor substrates, display devices and methods of manufacturing display devices

• US 9,245,937 B2
• Filed: 08/18/2014
• Issued: 01/26/2016
• Est. Priority Date: 10/15/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kim, Jae-Sik
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US14/461,669
• Publication Number:
  US 20150102317A1
• Time in Patent Office: 526 Days
• Field of Search: 257/40, 257/43, 438/149
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/88 Passivation; Containers; Encapsulations
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 71/231 by etching of existing layers
• CPC Class Codes: H10K 71/60 Forming conductive regions or layers, e.g. electrodes

Abstract

A thin film transistor substrate may include a gate electrode on a base substrate, a gate insulation layer covering the gate electrode on the base substrate, an active pattern on the gate insulation layer, an etch-stop layer pattern partially exposing the active pattern, a source electrode and a drain electrode in contact with a portion of the exposed active pattern, and an inorganic barrier layer on the source electrode, the drain electrode, and the etch-stop layer pattern. The active pattern may be superimposed over the gate electrode. The source electrode and the drain electrode may be superimposed over both ends of the gate electrode. The inorganic barrier layer may be in contact with a remaining portion of the exposed active pattern.

Claims

1. A thin film transistor substrate, comprising:

a gate electrode on a base substrate, the gate electrode including at least two ends;

a gate insulation layer covering the gate electrode on the base substrate;

an active pattern on the gate insulation layer, the active pattern including an oxide semiconductor and being superimposed over the gate electrode;

an etch-stop layer pattern including contact holes or openings through which the active pattern is partially exposed, the etch-stop layer pattern including a central portion and first and second peripheral portions, the first peripheral portion separated from the central portion by a first one of the contact holes or openings and the second peripheral portion separated from the central portion by a second one of the contact holes or openings, upper surfaces of the central portion and the first and second peripheral portions being substantially coplanar;

a source electrode and a drain electrode in contact with a portion of the exposed active pattern, the source electrode and the drain electrode being superimposed over respective ends of the gate electrode;

an inorganic barrier layer on the source electrode, the drain electrode, and the etch-stop layer pattern, the inorganic barrier layer including a metal oxide and being in direct contact with a remaining portion of the exposed active pattern; and

a planarization layer directly on the inorganic barrier layer, the planarization layer including a transparent organic material, wherein the source electrode and the drain electrode partially fill the contact holes or the openings, the inorganic barrier layer is in contact with a bottom of a remaining portion of the contact holes or the openings, and the planarization layer fills the remaining portion of the contact holes or the openings.

2. The thin film transistor substrate as claimed in claim 1, wherein the active pattern includes an oxide semiconductor.

3. The thin film transistor substrate as claimed in claim 1, wherein the planarization layer includes a polyimide-based resin, a siloxane-based resin or benzo cyclobutene (BCB).

4. The thin film transistor substrate as claimed in claim 1, wherein the inorganic barrier layer includes aluminum oxide, titanium oxide, or a combination thereof.

5. The thin film transistor substrate as claimed in claim 1, wherein the source electrode and the drain electrode are on the first and second peripheral portions, respectively, of the etch-stop layer pattern and partially fill the contact holes or the openings.

6. The thin film transistor substrate as claimed in claim 5, wherein the source electrode and the drain electrode are not superimposed on the central portion of the etch-stop layer pattern.

7. The thin film transistor substrate as claimed in claim 1, wherein the inorganic barrier layer has a thickness ranging from about 50 521 to about 200 Å

.

8. A display device, comprising:

a gate electrode on a base substrate, the gate electrode including at least two ends;

a gate insulation layer covering the gate electrode on the base substrate;

an active pattern on the gate insulation layer, the active pattern including an oxide semiconductor and being superimposed over the gate electrode;

an etch-stop layer pattern including contact holes or openings through which the active pattern is partially exposed, the etch-stop layer pattern including a central portion and first and second peripheral portions, the first peripheral portion separated from the central portion by a first one of the contact holes or openings and the second peripheral portion separated from the central portion by a second one of the contact holes or openings, upper surfaces of the central portion and the first and second peripheral portions being substantially coplanar;

a source electrode and a drain electrode in contact with a portion of the exposed active pattern, the source electrode and the drain electrode being superimposed over respective ends of the gate electrode;

an inorganic barrier layer on the source electrode, the drain electrode and the etch-stop layer pattern, the inorganic barrier layer including a metal oxide and being in direct contact with a remaining portion of the exposed active pattern;

a planarization layer directly on the inorganic barrier layer, the planarization layer including a transparent organic material;

a first electrode electrically connected to the drain electrode through the planarization layer and the inorganic barrier layer;

an organic light emitting layer on the first electrode; and

a second electrode on the organic light emitting layer, wherein the source electrode and the drain electrode partially fill the contact holes or the openings, the inorganic barrier layer is in contact with a bottom of a remaining portion of the contact holes or the openings, and the planarization layer fills the remaining portion of the contact holes or the openings.

9. The display device as claimed in claim 8, wherein the planarization layer includes a polyimide-based resin, a siloxane-based resin or benzocyclobutene (BCB).

10. The display device as claimed in claim 9, wherein the inorganic barrier layer includes aluminum oxide, titanium oxide, or a combination thereof.

11. A method of manufacturing a display device, comprising:

forming a gate electrode on a base substrate, the gate electrode including at least two ends;

forming a gate insulation layer covering the gate electrode on the base substrate;

forming an active pattern on the gate insulation layer, the active pattern being formed of an oxide semiconductor and being superimposed over the gate electrode;

forming an etch-stop layer pattern partially covering the active pattern and including contact holes or openings through which the active pattern is partially exposed, the etch-stop layer pattern including a central portion and first and second peripheral portions, the first peripheral portion separated from the central portion by a first one of the contact holes or openings and the second peripheral portion separated from the central portion by a second one of the contact holes or openings, upper surfaces of the central portion and the first and second peripheral portions being substantially coplanar;

forming a source electrode and a drain electrode in contact with a portion of the active pattern exposed by the etch-stop layer pattern, the source electrode and the drain electrode being superimposed over both ends of the gate electrode and partially filling the contact holes or the openings;

forming an inorganic barrier layer on the source electrode, the drain electrode and the etch-stop layer pattern, the inorganic barrier layer being formed of a metal oxide, the inorganic barrier layer being in direct contact with a remaining portion of the exposed active pattern and in contact with a bottom of a remaining portion of the contact holes or the openings;

forming a planarization layer directly on the inorganic barrier layer to fill the remaining portion of the contact holes or the openings, the planarization layer being formed of a transparent organic material;

forming a first electrode on the planarization layer, the first electrode being electrically connected to the drain electrode through the planarization layer and the inorganic barrier layer;

forming an organic light emitting layer on the first electrode; and

forming a second electrode on the organic light emitting layer.

12. The method as claimed in claim 11, wherein forming the etch-stop layer pattern includes:

forming an etch-stop layer covering the active pattern on the gate insulation layer; and

partially etching the etch-stop layer to form the contact holes or the openings partially exposing the active pattern.

13. The method as claimed in claim 12, wherein forming the source electrode and the drain electrode includes:

forming a first conductive layer filling the contact holes or the openings on the etch-stop layer pattern; and

partially removing a portion of the first conductive layer formed in the contact holes or the openings.

14. The method as claimed in claim 11, wherein forming the first electrode includes:

partially removing the planarization layer by an exposure process and a developing process to form a preliminary via hole;

removing a portion of the inorganic barrier layer exposed by the preliminary via hole to form a via hole exposing the drain electrode;

forming a second conductive layer on the planarization layer, sidewalls of the via hole, and a bottom surface of the via hole; and

patterning the second conductive layer.