Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered airgap field plates

• US 9,245,960 B2
• Filed: 02/08/2013
• Issued: 01/26/2016
• Est. Priority Date: 02/08/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Abou-Khalil, Michel J., Letavic, Theodore J., Luce, Stephen E., Stamper, Anthony K.
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Jiang, Fang-Xing
• Application Number:
  US13/762,450
• Publication Number:
  US 20140225186A1
• Time in Patent Office: 1,082 Days
• Field of Search: 257/60, 257/330, 257/342, 257/409, 438/270
• US Class Current: 1/1
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are embodiments of a lateral, extended drain, metal oxide semiconductor, field effect transistor (LEDMOSFET) having tapered dielectric field plates positioned laterally between conductive field plates and opposing sides of a drain drift region of the LEDMOSFET. Each dielectric field plate comprises, in whole or in part, an airgap. These field plates form plate capacitors that can create an essentially uniform horizontal electric field profile within the drain drift region so that the LEDMOSFET can exhibit a specific, relatively high, breakdown voltage (Vb). Tapered dielectric field plates that incorporate airgaps provide for better control over the creation of the uniform horizontal electric field profile within the drain drift region, as compared to tapered dielectric field plates without such airgaps and, thereby ensure that the LEDMOSFET exhibits the specific, relatively high, Vb desired. Also disclosed herein are embodiments of a method of forming such an LEDMOSFET.

Claims

1. A field effect transistor comprising:

an insulator layer;

a semiconductor body on said insulator layer, said semiconductor body being essentially rectangular in shape and having a bottom surface immediately adjacent to said insulator layer, a top surface opposite said bottom surface, opposing sidewalls, a first end and a second end opposite said first end, and said semiconductor body comprising;

a source region within said semiconductor body at said first end;

a drain region within said semiconductor body at said second end;

a channel region within said semiconductor body positioned laterally adjacent to said source region; and

a drain drift region within said semiconductor body extending laterally from said channel region to said drain region;

dielectric field plates on said insulator layer positioned laterally immediately adjacent to said opposing sidewalls, respectively, such that said drain drift region is positioned between and immediately adjacent to said dielectric field plates;

conductive field plates on said insulator layer positioned laterally immediately adjacent to said dielectric field plates such that each dielectric field plate is between said drain drift region and a conductive field plate,

said dielectric field plate having a width that increases along a length of said drain drift region from said channel region to said drain region such that a distance between said drain drift region and said conductive field plate increases along said length of said drain drift region,

said dielectric field plate comprising a cavity filled with any one of air and gas,

said cavity having an essentially triangular shaped cross-section through a plane that is parallel to said top surface of said semiconductor body, and

said conductive field plate being longer than said cavity and extending laterally beyond said cavity toward said drain region; and

,

a dielectric cap layer above and immediately adjacent to top surfaces of said conductive field plates and said semiconductor body, said dielectric cap layer further extending laterally over and covering said cavity.

2. The field effect transistor of claim 1, said cavity extending vertically to at least a top surface of said insulator layer and further having an essentially triangular shape defined by vertical surfaces of said semiconductor body at said drain drift region, of said conductive field plate and of an isolation region.

3. The field effect transistor of claim 2, wherein, within said cavity, said top surface of said insulator layer and said vertical surfaces of said semiconductor body, said conductive field plate and said isolation region are lined with a dielectric liner.

4. The field effect transistor of claim 1, said dielectric field plate further comprising isolation material, said cavity being within said isolation material such that said isolation material that physically separates said cavity from said conductive field plate and said drain drift region.

5. The field effect transistor of claim 1, said top surfaces of said conductive field plates and said semiconductor body being essentially co-planar.

6. The field effect transistor of claim 1, said drain drift region having an essentially uniform horizontal electric field profile from said channel region to said drain region and said dielectric field plates having predefined dimensions so that said field effect transistor has a specific drain-to-body breakdown voltage.

7. The field effect transistor of claim 1, each conductive field plate comprising one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

8. A field effect transistor comprising:

an insulator layer;

a semiconductor body on said insulator layer, said semiconductor body being essentially rectangular in shape and having a bottom surface immediately adjacent to said insulator layer, a top surface opposite said bottom surface, opposing sidewalls, a first end and a second end opposite said first end, and said semiconductor body comprising;

a source region within said semiconductor body at said first end;

a drain region within said semiconductor body at said second end;

a channel region within said semiconductor body on said insulator layer and positioned laterally adjacent to said source region; and

a drain drift region within said semiconductor body extending laterally from said channel region to said drain region;

an isolation region on said insulator layer and positioned laterally immediately adjacent to said opposing sidewalls, said first end and said second end of said semiconductor body, said isolation region comprising isolation material;

conductive field plates extending through said isolation region to said insulator layer such that portions of said isolation region are positioned between said conductive field plates and said opposing sidewalls of said semiconductor body, respectively, such that said drain drift region is positioned between and immediately adjacent to said portions of said isolation region,

each portion of said isolation region that is positioned between a corresponding one of said conductive field plates and an opposing sidewall of said semiconductor body forming a dielectric field plate,

said dielectric field plate having a width that increases along a length of said drain drift region from said channel region to said drain region such that a distance between said drain drift region and said corresponding one of said conductive field plates increases along said length of said drain drift region,

said dielectric field plate having a cavity that extends through said isolation region to said insulator layer and that is physically separated from said corresponding one of said conductive field plates and said opposing sidewall of said semiconductor body by said isolation material,

said cavity having a triangular shaped cross-section through a plane that is parallel to said top surface of said semiconductor body,

said corresponding one of said conductive field plates being longer than said cavity and extending laterally beyond said cavity toward said drain region; and

,

a dielectric cap layer above and immediately adjacent to top surfaces of said conductive field plates, said semiconductor body, and said isolation region, said dielectric cap layer further extending laterally over and covering said cavity.

9. The field effect transistor of claim 8, said top surfaces of said conductive field plates, said semiconductor body, and said isolation region being essentially co-planar.

10. The field effect transistor of claim 8, said cavity being centered within said portion of said isolation region.

11. The field effect transistor of claim 10, said cavity having a smaller triangular shape than said portion of said isolation region.

12. The field effect transistor of claim 8, said drain drift region having an essentially uniform horizontal electric field profile from said channel region to said drain region and said dielectric field plate having predefined dimensions so that said field effect transistor has a specific drain-to-body breakdown voltage.

13. The field effect transistor of claim 8, each conductive field plate comprising one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

14. A field effect transistor comprising:

an insulator layer

a silicon body on said insulator layer, said silicon body having an essentially rectangular shape and having a bottom surface, a top surface opposite said bottom surface, opposing sidewalls, a first end and a second end opposite said first end, and said silicon body comprising;

a source region within said silicon body at said first end;

a drain region within said silicon body at said second end;

a channel region within said silicon body positioned laterally adjacent to said source region; and

a drain drift region within said silicon body extending laterally from said channel region to said drain region;

dielectric field plates on said insulator layer positioned laterally immediately adjacent to said opposing sidewalls, respectively, such that said drain drift region is positioned between and immediately adjacent to said dielectric field plates;

conductive field plates on said insulator layer positioned laterally immediately adjacent to said dielectric field plates such that each dielectric field plate is between said drain drift region and a conductive field plate,

said dielectric field plate having a width that increases along a length of said drain drift region from said channel region to said drain region such that a distance between said drain drift region and said conductive field plate increases along said length of said drain drift region,

said dielectric field plate comprising a cavity filled with any one of air and gas,

said cavity having a triangular shaped cross-section through a plane that is parallel to said top surface of said silicon body, and

said conductive field plate being longer than said cavity and extending laterally beyond said cavity toward said drain region; and

,

a dielectric cap layer above and immediately adjacent to top surfaces of said conductive field plates and said silicon body, said dielectric cap layer further extending laterally over and covering said cavity.

15. The field effect transistor of claim 14, said dielectric field plate further comprising isolation material, said cavity being within said isolation material such that said isolation material physically separates said cavity from said conductive field plate and said drain drift region.

16. The field effect transistor of claim 14, said top surfaces of said conductive field plates and said silicon body being essentially co-planar.

17. The field effect transistor of claim 14, said drain drift region having an essentially uniform horizontal electric field profile from said channel region to said drain region and said dielectric field plates having predefined dimensions so that said field effect transistor has a specific drain-to-body breakdown voltage.

18. The field effect transistor of claim 14, each conductive field plate comprising one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.

19. A field effect transistor comprising:

an insulator layer;

a silicon body on said insulator layer, said silicon body being essentially rectangular in shape and having a bottom surface immediately adjacent to said insulator layer, a top surface opposite said bottom surface, opposing sidewalls, a first end and a second end opposite said first end, and said silicon body comprising;

a source region within said silicon body at said first end;

a drain region within said silicon body at said second end;

a channel region within said silicon body positioned laterally adjacent to said source region; and

a drain drift region within said silicon body extending laterally from said channel region to said drain region;

an isolation region on said insulator layer and positioned laterally immediately adjacent to said opposing sidewalls, said first end and said second end of said silicon body, said isolation region comprising isolation material;

conductive field plates extending through said isolation region and to said insulator layer such that portions of said isolation region are positioned between said conductive field plates and said opposing sidewalls of said silicon body, respectively, and such that said drain drift region is positioned between and immediately adjacent to said portions of said isolation region,

each portion of said isolation region that is positioned between a corresponding one of said conductive field plates and an opposing sidewall of said silicon body forming a dielectric field plate,

said dielectric field plate having a width that increases along a length of said drain drift region from said channel region to said drain region such that a distance between said drain drift region and said corresponding one of said conductive field plates increases along said length of said drain drift region,

said dielectric field plate having a cavity that extends through said portion of said isolation region to said insulator layer and that is physically separated from said corresponding one of said conductive field plates and said opposing sidewall of said silicon body by said isolation material,

said cavity having a triangular shaped cross-section through a plane that is parallel to said top surface of said silicon body,

said corresponding one of said conductive field plates being longer than said cavity and extending laterally beyond said cavity toward said drain region; and

,

a dielectric cap layer above and immediately adjacent to top surfaces of said conductive field plates, said silicon body, and said isolation region, said dielectric cap layer further extending laterally over and covering said cavity.

20. The field effect transistor of claim 19, said top surfaces of said conductive field plates, said silicon body and said isolation region being essentially co-planar.

21. The field effect transistor of claim 19, said cavity being centered with said portion of said isolation region.

22. The field effect transistor of claim 21, said cavity having a smaller triangular shape than said portion of said isolation region.

23. The field effect transistor of claim 19, said drain drift region having an essentially uniform horizontal electric field profile from said channel region to said drain region and said dielectric field plate having predefined dimensions so that said field effect transistor has a specific drain-to-body breakdown voltage.

24. The field effect transistor of claim 19, each conductive field plate comprising one of a discrete semiconductor shape, a discrete metal shape, and an extension of a gate structure traversing said channel region.