Insulated gate semiconductor device structure

• US 9,245,963 B2
• Filed: 10/14/2014
• Issued: 01/26/2016
• Est. Priority Date: 06/27/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M, Padmanabhan, Balaji, Venkatraman, Prasad, Burke, Peter A
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US14/514,017
• Publication Number:
  US 20150028414A1
• Time in Patent Office: 469 Days
• Field of Search: 257/330, 257/E29.257, 257/332, 257/E29.2, 257/401, 438/589, 438/270, 438/259, 438/271
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In one embodiment, a vertical insulated-gate field effect transistor includes a shield electrode formed in trench structure within a semiconductor material. A gate electrode is isolated from the semiconductor material using gate insulating layers. Before the shield electrode is formed, spacer layers can be used form shield insulating layers along portions of the trench structure. The shield insulating layers are thicker than the gate insulating layers. In another embodiment, the shield insulating layers have variable thickness.

Claims

1. A semiconductor device comprising:

a region of semiconductor material having a major surface;

a trench extending from the major surface;

a first layer overlying surfaces of the trench;

a second layer adjacent the first layer, where the second layer comprises a material different than the first layer, and where the second layer is disposed in a lower portion of the trench and not an upper portion of the trench, and where the second layer is discontinuous in proximity to a lower surface of the trench;

a first region comprising a material different than the second layer in proximity to the lower surface of the trench;

a first electrode in the lower portion of the trench and adjacent portions of the second layer and the first region, where portions of the first layer are between the first electrode and the region of semiconductor material;

a dielectric layer above the first electrode; and

a second electrode adjacent the first layer and the dielectric layer, where at least a portion of the second electrode is within the trench.

2. The structure of claim 1 further comprising:

a body region adjoining the trench; and

a source region adjoining the body region and the trench, where the first layer comprises a gate dielectric layer, and where the first electrode comprises a shield electrode, and where the second electrode comprises a gate electrode.

3. The structure of claim 1, where the first layer comprise silicon oxide.

4. The structure of claim 3, where the second layer comprises silicon nitride.

5. The structure of claim 1 further comprising:

a body region adjoining the trench; and

a source region adjoining the body region and the trench, where the source region comprises an extension portion adjoining the trench and a central portion adjoining the extension portion, and where the central portion is shallower than the extension portion.

6. The structure of claim 1, where the first region comprises a thickness that increases along sidewall surfaces of the first electrode, and where the thickness is greatest in proximity to a lowest portion of the trench.

7. The structure of claim 1, where the first electrode comprises a stepped shape in cross-sectional view such that the first electrode decreases in width and is narrower in proximity to the lower surface of the trench.

8. A semiconductor device structure comprising:

a trench extending into a semiconductor region;

a shield electrode disposed in a lower portion of the trench;

a first dielectric layer disposed in both the lower portion of the trench and an upper portion of the trench and disposed, at least in part, between a second dielectric layer and the semiconductor region;

the second dielectric layer disposed, at least in part, between the first dielectric layer and a third dielectric layer, and disposed in the lower portion of the trench but not disposed in the upper portion of the trench, wherein the second dielectric layer is discontinuous in proximity to a lower surface of the trench;

the third dielectric layer disposed in the lower portion of the trench and not disposed in the upper portion of the trench; and

a fourth dielectric layer disposed between the shield electrode and a gate electrode, the gate electrode being disposed in the upper portion of the trench.

9. The structure of claim 8, where

the first dielectric layer comprises a first oxide layer;

the second dielectric layer comprises a nitride layer; and

the third dielectric layer comprises a second oxide layer.

10. The structure of claim 9, wherein the fourth dielectric layer comprises a third oxide layer.

11. The structure of claim 8 further comprising:

a body region adjoining the trench; and

a source region adjoining the body region and the trench, where the source region comprises an extension portion adjoining the trench and a central portion adjoining the extension portion, and where the central portion is shallower than the extension portion.

12. The structure of claim 8, where the shield electrode comprises a stepped shape in cross-sectional view such that the first electrode decreases in width and is narrower in proximity to the lower surface of the trench.

13. The structure of claim 8, where the second dielectric layer comprises a material configured to inhibit growth of oxide along a portion of the lower surface of the trench.

14. The structure of claim 8, where the first dielectric layer has a thickness from about 0.01 microns to about 0.05 microns.

15. The structure of claim 8, where the second dielectric layer has a thickness from about 0.01 microns to about 0.05 microns.

16. The structure of claim 8, where the third dielectric layer has a thickness from about 0.03 microns to about 0.05 microns, and the fourth dielectric layer has a thickness from about 0.1 microns to about 0.3 microns.

17. The structure of claim 8 further comprising a dielectric region along a lower segment of the trench.

18. The structure of claim 17, where the dielectric region comprises an oxide.

19. The structure of claim 18, where the oxide has a thickness from 0.1 microns to about 0.2 microns.

20. A semiconductor device comprising:

a region of semiconductor material having a major surface;

a trench extending from the major surface into the region of semiconductor material;

a first dielectric layer overlying surfaces of the trench;

a second dielectric layer adjacent the first dielectric layer, where the second dielectric layer comprises a material different than the first dielectric layer, and where the second dielectric layer is disposed in a lower portion of the trench and not an upper portion of the trench, and where the second dielectric layer is discontinuous in proximity to a lower surface of the trench;

a first electrode in the lower portion of the trench and adjacent portions of the second dielectric layer and the first region, where portions of the first dielectric layer are between the first electrode and the region of semiconductor material;

a third dielectric layer above the first electrode; and

a second electrode adjacent the first dielectric layer and the third dielectric layer, where at least a portion of the second electrode is within the trench.

21. The device of claim 20 further comprising a fourth dielectric layer disposed between the second dielectric layer and the first electrode, wherein the fourth dielectric layer is disposed in the lower portion of the trench and not disposed in the upper portion of the trench.

22. The device of claim 21, where

the first dielectric layer comprises a first oxide layer;

the second dielectric layer comprises a nitride layer;

the third dielectric layer comprises a second oxide layer; and

the fourth dielectric layer comprises a third oxide layer.

23. The device of claim 20 further comprising a first dielectric region comprising a material different than the second dielectric layer in proximity to the lower surface of the trench.