Method for manufacturing semiconductor device

• US 9,245,972 B2
• Filed: 09/03/2013
• Issued: 01/26/2016
• Est. Priority Date: 09/03/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Shin-Chi, Li, Chih-Yueh, Lu, Shui-Yen, Pai, Yuan-Chi, Chuang, Fong-Lung
• Primary Examiner(s): Perkins, Pamela E
• Application Number:
  US14/016,393
• Publication Number:
  US 20150064861A1
• Time in Patent Office: 875 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A method for manufacturing a semiconductor device is provided. A substrate having a first gate and a second gate respectively formed in a first region and a second region is provided. An underlayer is formed on the substrate to cover the first gate in the first region and the second gate in the second region. A patterned mask with a predetermined thickness is formed on the underlayer in the first region. The underlayer corresponding to the second gate in the second region is removed by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate.

Claims

1. A method for manufacturing a semiconductor device, comprising:

providing a substrate having a first gate and a second gate respectively formed in a first region and a second region;

forming an underlayer on the substrate to cover the first gate in the first region and the second gate in the second region;

forming a patterned mask with a predetermined thickness on the underlayer in the first region; and

removing the underlayer corresponding to the second gate in the second region by the patterned mask to expose the second gate, wherein the underlayer corresponding to the first gate in the first region is partially consumed to expose part of the first gate, a top surface of the underlayer remained in the first region has substantially equal height for forming a flat plane, and the top surface of the underlayer remained in the first region is lower than a top surface of the first gate.

2. The method according to claim 1, after removing the underlayer in the second region to expose the second gate, the method further comprising:

forming a plurality of recesses at the substrate adjacent the second gate in the second region, wherein a first cap layer of the first gate and a second cap layer of the second gate are exposed and consumed simultaneously during formation of the recesses, and a remained thickness of the first cap layer and a remained thickness of the second cap layer are substantially the same.

3. The method according to claim 2, wherein the first cap layer of the first gate and the second cap layer of the second gate are consumed simultaneously, and the exposed first and second cap layers are higher than the top surface of the underlayer.

4. The method according to claim 2, after forming the recesses at the substrate adjacent the second gate in the second region, the method further comprising:

removing the underlayer in the first region; and

growing an epitaxial layer at the recesses.

5. The method according to claim 4, after removing the underlayer in the first region, the method further comprising:

removing the first cap layer of the first gate and the second cap layer of the second gate.

6. The method according to claim 5, wherein the first cap layer and the second cap layer are removed by dry etching.

7. The method according to claim 4, after removing the underlayer in the first region, the method further comprising:

forming a planarization layer on the substrate to cover the first gate and the second gate;

partially removing the planarization layer to expose the first cap layer of the first gate and the second cap layer of the second gate; and

removing the first cap layer of the first gate and the second cap layer of the second gate.

8. The method according to claim 7, wherein the planarization layer is etched back to expose the first and the second cap layers.

9. The method according to claim 1, wherein when the underlayer corresponding to the second gate in the second region is removed, a portion of the underlayer substantially above a first cap layer of the first gate is removed.

10. The method according to claim 1, wherein when the underlayer corresponding to the second gate in the second region is removed, the top surface of the underlayer in the first region is substantially aligned with a top surface of a first cap layer of the first gate.

11. The method according to claim 1, wherein when the underlayer corresponding to the second gate in the second region is removed, the top surface of the underlayer in the first region is lower than a top surface of a first cap layer of the first gate.

12. The method according to claim 1, wherein a disposal layer is formed on the substrate and covers the first gate and the second gate.

13. The method according to claim 12, wherein when the underlayer corresponding to the second gate in the second region is removed, a portion of the disposal layer surrounding a top portion of the first gate is exposed.

14. The method according to claim 1, wherein a first gate comprises:

a first dielectric layer formed on the substrate;

a first conductive layer formed on the first dielectric layer; and

a first cap layer formed on the first conductive layer.

15. The method according to claim 14, wherein the first dielectric layer is a single dielectric layer or a multi-dielectric layer, the first conductive layer is a polysilicon layer, and the first cap layer is a hardmask layer.

16. The method according to claim 1, wherein a second gate in the second region comprises:

a second dielectric layer formed on the substrate;

a second conductive layer formed on the second dielectric layer; and

a second cap layer formed on the second conductive layer.

17. The method according to claim 16, wherein the second dielectric layer is a single dielectric layer or a multi-dielectric layer, the second conductive layer is a polysilicon layer, and the second cap layer is a hardmask layer.

18. The method according to claim 1, wherein the first region is an NMOS region, and the second region is a PMOS region.

19. The method according to claim 1, wherein the first region is a PMOS region, and the second region is an NMOS region.