MOSFET with curved trench feature coupling termination trench to active trench

• US 9,245,994 B2
• Filed: 02/07/2014
• Issued: 01/26/2016
• Est. Priority Date: 02/07/2013
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kawahara, Hideaki, Kocon, Christopher Boguslaw, Molloy, Simon John, Neilson, John Manning Savidge
• Primary Examiner(s): Henry, Caleb
• Assistant Examiner(s): AMER, MOUNIR S
• Application Number:
  US14/175,456
• Publication Number:
  US 20140217497A1
• Time in Patent Office: 718 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches. The active area trenches and termination trenches include a trench dielectric liner and electrically conductive filler material filled field plates. A gate is over the drain drift region between active area trenches. A body region of a second conductivity abuts the active region trenches. A source of the first conductivity type is in the body region on opposing sides of the gate. A vertical drain drift region uses the drift region below the body region. A first and second curved trench feature couples the field plate of the first and second termination trench to field plates of active area trenches.

Claims

1. A semiconductor device, comprising:

a substrate including a semiconductor surface;

a metal oxide semiconductor field effect transistor (MOSFET) in and on said semiconductor surface which provides a drift region of a first conductivity type, said MOSFET including;

a plurality of active area trenches disposed in said drift region;

a first and a second termination trench disposed in said drift region each parallel to and together sandwiching said plurality of active area trenches;

wherein each of said plurality of active area trenches and said first and said second termination trench include a trench dielectric liner and an electrically conductive filler material as a field plate;

at least one gate disposed over said drift region between said plurality of active area trenches;

a body region of a second conductivity type, opposite from said first conductivity type, disposed in said drift region abutting said plurality of active area trenches,

a source of said first conductivity type formed in said body region on opposing sides of said gate;

a vertical drain drift region using said drift region below said body region having a drain contact on said substrate, and

a first curved trench feature laterally extending from the first termination trench to a first of said plurality of active area trenches to couple said field plate of said first termination trench to said field plate of the first of said plurality of active area trenches, and a second curved trench feature laterally extending from the second termination trench to a second of said plurality of active area trenches to couple said field plate of said second termination trench to said field plate of the second of said plurality of active area trenches, wherein laterally extending regions of the first curved trench feature include curved regions and wherein laterally extending regions of the second curved trench feature include curved regions.

2. The semiconductor device of claim 1, wherein said electrically conductive filler material comprises doped polysilicon.

3. The semiconductor device of claim 2, wherein said doped polysilicon comprises n+ doped polysilicon.

4. The semiconductor device of claim 2, wherein said doped polysilicon comprises p+ doped polysilicon.

5. The semiconductor device of claim 1, wherein said first and said second curved trench features in curved regions thereof all provide at least one of an angle of least 110 degrees and a radius of curvature (ROC) of ≧

3 μ

m.

6. The semiconductor device of claim 5, wherein said first and said second curved trench features each have a trench width≧

20% more than a width of said plurality of active area trenches and a width of said first and said second termination trenches.

7. The semiconductor device of claim 1, wherein said first conductivity type is n-type and said MOSFET is an n-channel MOSFET.

8. The semiconductor device of claim 1, wherein said gate is a split gate having central openings in a central area between ones of said plurality of active area trenches.

9. The semiconductor device of claim 1, wherein said trench dielectric liner comprises silicon oxide, silicon nitride, or silicon oxynitride.

10. The semiconductor device of claim 1, wherein said semiconductor surface comprises silicon.

11. The semiconductor device of claim 1, wherein the first curved trench feature laterally extends from the first termination trench to the first of said plurality of active area trenches without forming a 90°

angle and wherein the second curved trench feature laterally extends from the second termination trench to the second of said plurality of active area trenches without forming a 90°

angle.

12. A semiconductor device, comprising:

a silicon substrate including a silicon comprising surface;

a metal oxide semiconductor field effect transistor (MOSFET) in and on said silicon comprising surface which provides an n-drift region, said MOSFET including;

a plurality of active area trenches disposed in said n-drift region;

a first and a second termination trench disposed in said n-drift region each parallel to and together sandwiching said plurality of active area trenches;

wherein each of said plurality of active area trenches and said first and said second termination trench include a trench dielectric liner and an electrically conductive filler material as a field plate;

at least one gate disposed over said n-drift region between said plurality of active area trenches;

a p-body region disposed in said n-drift region abutting said plurality of active area trenches,

an n-type source formed in said p-body region on opposing sides of said gate;

a vertical drain drift region using said n-drift region below said p-body region having a drain contact on said silicon substrate, and

at least a first curved trench feature providing a laterally extending connection between the first termination trench and a first of the plurality of active area trenches to couple said field plate of said first termination trench to said field plate of the first of said plurality of active area trenches, and at least a second curved trench feature providing a laterally extending connection between the second termination trench and a second of the plurality of active area trenches to couple said field plate of said second termination trench to said field plate of the second of said plurality of active area trenches.

13. The semiconductor device of claim 12, wherein said first and second curved trench features in curved regions thereof all provide at least one of an angle of at least 110 degrees and a radius of curvature (ROC) of ≧

3 μ

m.

14. The semiconductor device of claim 12, wherein said electrically conductive filler material comprises n+ doped polysilicon.

15. The semiconductor device of claim 12, wherein said electrically conductive filler material comprises p+ doped polysilicon.

16. A semiconductor device, comprising:

a substrate including a semiconductor surface;

a metal oxide semiconductor field effect transistor (MOSFET) in and on said semiconductor surface which provides a drift region of a first conductivity type, said MOSFET including;

a plurality of active area trenches disposed in said drift region;

a first and a second termination trench disposed in said drift region each parallel to and together sandwiching said plurality of active area trenches;

wherein each of said plurality of active area trenches and said first and said second termination trench include a trench dielectric liner and an electrically conductive filler material as a field plate;

at least one gate disposed over said drift region between said plurality of active area trenches;

a body region of a second conductivity type, opposite from said first conductivity type, disposed in said drift region abutting said plurality of active area trenches,

a source of said first conductivity type formed in said body region on opposing sides of said gate;

a vertical drain drift region using said drift region below said body region having a drain contact on said substrate, and

a first curved connection trench laterally extending between the first termination trench and a first of said plurality of active area trenches and a second curved connection trench laterally extending between the second termination trench and a second of said plurality of active area trenches, wherein the first curved connection includes no 90°

angles and the second curved connection includes no 90°

angles.