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Vertical channel transistor structure and manufacturing method thereof

  • US 9,246,015 B2
  • Filed: 09/28/2010
  • Issued: 01/26/2016
  • Est. Priority Date: 10/11/2006
  • Status: Active Grant
First Claim
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1. A vertical channel transistor array, comprising:

  • a substrate;

    a plurality of channels protruded from the substrate;

    a plurality of cap layers on the plurality of channels, wherein cap layers in the plurality of cap layers and channels in the plurality of channels substantially have the same width, wherein the cap layers comprise a silicon nitride (SiN) layer positioned on a silicon dioxide (SiO2) layer, and the SiN layer has a top surface and two vertical surfaces;

    a multilayer charge trapping layer directly on the top surface and the two vertical surfaces of the SiN layer of the plurality of cap layers and on two vertical surfaces of the channels in the plurality of channels, the multilayer charge trapping layer including at least a first oxide layer, a first charge trapping layer on the first oxide layer, and a second oxide layer on the first charge trapping layer;

    a plurality of word lines, word lines in the plurality of word lines straddling on the multilayer charge trapping layer and positioned on the two vertical surfaces of the channels in the plurality of channels; and

    sources and drains respectively positioned on the two vertical sides of the channels in the plurality of channels,wherein a channel in the plurality of channels in between adjacent ones of the sources and the drains, and in between the substrate and a word line of the plurality of word lines, supports only one transistor,wherein the array is arranged as a plurality of series-connected NAND strings having opposite ends that end in transistors, and every transistor in the plurality of series-connected NAND strings includes one of the cap layers in the plurality of cap layers that comprises the silicon dioxide (SiO2) layer and the silicon nitride (SiN) layer.

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