Vertical channel transistor structure and manufacturing method thereof

• US 9,246,015 B2
• Filed: 09/28/2010
• Issued: 01/26/2016
• Est. Priority Date: 10/11/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hsu, Tzu-Hsuan, Shih, Yen-Hao, Wu, Chia-Wei
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Booker, Vicki B
• Application Number:
  US12/892,044
• Publication Number:
  US 20110012192A1
• Time in Patent Office: 1,946 Days
• Field of Search: 257/328, 257/E29.262, 257/E21.679
• US Class Current: 1/1
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Claims

1. A vertical channel transistor array, comprising:

a substrate;

a plurality of channels protruded from the substrate;

a plurality of cap layers on the plurality of channels, wherein cap layers in the plurality of cap layers and channels in the plurality of channels substantially have the same width, wherein the cap layers comprise a silicon nitride (SiN) layer positioned on a silicon dioxide (SiO2) layer, and the SiN layer has a top surface and two vertical surfaces;

a multilayer charge trapping layer directly on the top surface and the two vertical surfaces of the SiN layer of the plurality of cap layers and on two vertical surfaces of the channels in the plurality of channels, the multilayer charge trapping layer including at least a first oxide layer, a first charge trapping layer on the first oxide layer, and a second oxide layer on the first charge trapping layer;

a plurality of word lines, word lines in the plurality of word lines straddling on the multilayer charge trapping layer and positioned on the two vertical surfaces of the channels in the plurality of channels; and

sources and drains respectively positioned on the two vertical sides of the channels in the plurality of channels,

wherein a channel in the plurality of channels in between adjacent ones of the sources and the drains, and in between the substrate and a word line of the plurality of word lines, supports only one transistor,

wherein the array is arranged as a plurality of series-connected NAND strings having opposite ends that end in transistors, and every transistor in the plurality of series-connected NAND strings includes one of the cap layers in the plurality of cap layers that comprises the silicon dioxide (SiO2) layer and the silicon nitride (SiN) layer.

2. The vertical channel transistor array according to claim 1, further comprising a thick silicon oxide (SiO) layer positioned on the substrate.

3. The vertical channel transistor array according to claim 1, wherein the first charge trapping layer is made from SiN or aluminum oxide (Al₂O₃).

4. The vertical channel transistor array according to claim 1, wherein the substrate is a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.

5. The vertical channel transistor array according to claim 1, wherein the gate is made from N+ polysilicon, P+ polysilicon, or metal.

6. The vertical channel transistor array according to claim 1, wherein a line width of the channel approximately ranges between 10 nm˜

60 nm.