Silicon carbide semiconductor device

• US 9,246,016 B1
• Filed: 03/25/2015
• Issued: 01/26/2016
• Est. Priority Date: 07/02/2014
• Status: Active Grant

• Current Assignee: Shanghai Hestia Power Inc.
• Original Assignee: Hestia Power, Inc.
• Inventors: Yen, Cheng-Tyng, Hung, Chien-Chung, Lee, Chwan-Ying, Lee, Lurng-Shehng
• Primary Examiner(s): Coleman, William
• Assistant Examiner(s): LY, KIEN C
• Application Number:
  US14/668,299
• Publication Number:
  US 20160005883A1
• Time in Patent Office: 307 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0485 Ohmic electrodes
• CPC Class Codes: H01L 21/0495 Schottky electrodes
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A silicon carbide (SiC) semiconductor device having a metal oxide semiconductor field effect transistor (MOSFET) and integrated with an anti-parallelly connected Schottky diode includes: a substrate, an n-drift layer, a plurality of doped regions, a gate dielectric layer, a gate electrode, an inter-layer dielectric layer, a plurality of source openings, a plurality of junction openings, a plurality of gate openings, a first metal layer and a second metal layer. The second metal layer at the junction openings forms the Schottky diode.

Claims

1. A silicon carbide (SiC) semiconductor device, comprising:

a substrate, having heavily doped n-type;

an n-drift layer, disposed on the substrate, having lightly doped n-type compared to the substrate;

a plurality of doped regions, disposed at the n-drift layer, spaced from each other and formed a junction field effect transistor (JFET) region therebetween, each of the doped regions comprising a p-well, a heavily doped n-type (n+) region located in the p-well, and a heavily doped p-type (p+) region located in the p-well and surrounded by the n+ region;

a gate dielectric layer, disposed on the n-drift layer;

a gate electrode, disposed on the gate dielectric layer;

an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode;

a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the n+ region and the p+ region and are separated by the gate electrode and the inter-layer dielectric layer;

a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the JFET region and the doped regions are separated by the gate electrode and the inter-layer dielectric layer;

a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode;

a first metal layer, disposed at a bottom of the source openings, formed an Ohmic contact with the surface portion of the n+ region and the p+ region; and

a second metal layer, comprising a first portion and a second portion wherein the first portion covers the source openings and the junction openings is electrically connected to the first metal layer and forms a Schottky contact with the surface portion the JFET region;

the second portion covers the gate openings and is electrically insulated from the first portion.

2. The SiC semiconductor device of claim 1, wherein the p+ region is surrounded by the p-well and the n+ region, and a part or all of the p+ region overlaps with the p-well.

3. The SiC semiconductor device of claim 1, wherein the substrate is a 4H-SiC substrate.

4. The SiC semiconductor device of claim 1, wherein the first metal layer is a silicide or a combination of silicides of a material selected from a group consisting of nickel, titanium and aluminum.

5. The SiC semiconductor device of claim 1, wherein the second metal layer is selected from a group or a combination consisting of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, an aluminum copper alloy and an aluminum silicon copper alloy.

6. The SiC semiconductor device of claim 1, wherein a planar contour of the p-well is a square, a rectangle or a hexagon.

7. The SiC semiconductor device of claim 1, wherein a planar contour of the junction openings is a quadrilateral, a hexagon, an octagon or a circle.

8. A silicon carbide (SiC) semiconductor device, comprising:

a substrate, having heavily doped n-type;

a n-drift layer, disposed on the substrate, having lightly doped n-type compared to the substrate;

a plurality of first doped regions, disposed at the n-drift layer, each of the first doped regions comprising a first p-well, a first n+ region arranged in the first p-well, and a first p+ region arranged in the first p-well and surrounded by the first n+ region;

a plurality of second doped regions, disposed at the n-drift layer and spaced from the first doped regions to form a JFET region between the first doped region and the second doped region, each of the second doped regions comprising a second p-well surrounding a non-p-well region, and a second p+ region surrounding the non-p-well region and a part or all of the p+ region overlaps with the second p-well;

a gate dielectric layer, disposed on the n-drift layer;

a gate electrode, disposed on the gate dielectric layer;

an inter-layer dielectric layer, disposed on the gate dielectric layer and the gate electrode;

a plurality of source openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the first n+ region and the first p+ region, and are separated by the gate electrode and the inter-layer dielectric layer;

a plurality of junction openings, penetrating through the inter-layer dielectric layer and the gate dielectric layer to a surface portion of the second doped region, and are separated by the gate electrode and the inter-layer dielectric layer;

a plurality of gate openings, penetrating through the inter-layer dielectric layer to a surface portion of the gate electrode;

a first metal layer, disposed at a bottom of the source openings, formed an Ohmic contact with the surface portion of the first n+ region and the first p+ region; and

a second metal layer, comprising a first portion and a second portion wherein the first portion covers the source openings and the junction openings and is electrically connected to the first metal layer and forms a Schottky contact with a surface portion of the non-p-well region, the second portion covers the gate openings and is electrically insulated from the first portion.

9. The SiC semiconductor device of claim 8, wherein the first p+ region is surrounded by the first p-well and the first n+ region, and a part or all of the first p+ region overlaps with the first p-well.

10. The SiC semiconductor device of claim 8, wherein each of the second doped regions further comprises a second n+ region arranged in the second p-well and adjacent to the second p+ region.

11. The SiC semiconductor device of claim 8, wherein the substrate is a 4H-SiC substrate.

12. The SiC semiconductor device of claim 8, wherein the first metal layer is a silicide or a combination of silicides of a material selected from a group consisting of nickel, titanium and aluminum.

13. The SiC semiconductor device of claim 8, wherein the second metal layer is selected from a group or a combination consisting of titanium, molybdenum, nickel, aluminum, titanium silicide, molybdenum silicide, nickel silicide, aluminum silicide, titanium nitride, an aluminum copper alloy and an aluminum silicon copper alloy.

14. The SiC semiconductor device of claim 8, wherein a planar contour of the first p-well is a square, a rectangle or a hexagon, and a planar contour of the second p-well is a square, a rectangle or a hexagon.

15. The SiC semiconductor device of claim 8, wherein a planar contour of the junction openings is a quadrilateral, a hexagon, an octagon or a circle.