Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states

• US 9,246,089 B2
• Filed: 12/31/2013
• Issued: 01/26/2016
• Est. Priority Date: 12/19/2002
• Status: Expired due to Fees

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Herner, Scott Brad, Walker, Andrew
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): GOODWIN, DAVID J
• Application Number:
  US14/145,614
• Publication Number:
  US 20140110660A1
• Time in Patent Office: 756 Days
• Field of Search: 438/593, 257/313, 257/314, 257/315
• US Class Current: 1/1
• CPC Class Codes: G11C 11/39 using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

Claims

1. A programmable memory cell comprising:

a first conductor extending in a first direction;

a vertical pillar consisting essentially of semiconductor material and conductivity-enhancing dopants and having a top surface and a bottom surface; and

a second conductor above the first conductor extending in a second direction different from the first direction, wherein;

the vertical pillar is disposed between the first and second conductors,

the top surface and the bottom surface are in electrical contact with the first and second conductors,

the vertical pillar comprises a silicon-germanium alloy and has a bottom region and a center region, the bottom region having a higher ratio of silicon to germanium than the center region,

no dielectric rupture antifuse is disposed between the first and second conductors, and

the programmable memory cell has a high impedance state and conducts unprogrammed current during application of a read voltage and has a low impedance state and conducts programmed current after application of a programming voltage and then the read voltage.

2. The memory cell of claim 1 wherein the vertical pillar functions as a junction diode.

3. The memory cell of claim 2 wherein the vertical pillar comprises a heavily doped p-type region and a heavily doped n-type region.

4. The memory cell of claim 1 wherein the vertical pillar comprises doped regions of one conductivity type only.

5. The memory cell of claim 4 wherein the vertical pillar functions as a resistor.

6. The memory cell of claim 1 wherein the read voltage is between about 0.5 volts and about 4 volts.

7. The memory cell of claim 6 wherein the read voltage is between about 0.8 volts and about 3 volts.

8. The memory cell of claim 1 wherein the read voltage is between about 1 volt and about 2 volts.

9. The memory cell of claim 1 wherein the memory cell is programmed by application of the programming voltage, the programming voltage between about 2 volts and about 18 volts.

10. The memory cell of claim 9 wherein the memory cell is programmed by application of the programming voltage, the programming voltage between about 2.5 volts and about 8 volts.

11. The memory cell of claim 10 wherein the memory cell is programmed by application of the programming voltage, the programming voltage between about 3 volts and about 5 volts.

12. The memory cell of claim 1 wherein the first or the second conductor does not comprise semiconductor material.

13. The memory cell of claim 12 wherein the first or the second conductor comprises a metal.

14. The memory cell of claim 13 wherein the first or the second conductor comprises tungsten.

15. The memory cell of claim 1 wherein the difference between the unprogrammed current and the programmed current is at least two orders of magnitude.

16. The memory cell of claim 15 wherein the difference between the unprogrammed current and the programmed current is at least three orders of magnitude.

17. The memory cell of claim 1 wherein the unprogrammed current is less than or equal to about 3.5×

10-8 amps.

18. The memory cell of claim 1 wherein the unprogrammed current density is less than or equal to about 4.4×

10-6 amp/micron2.

19. The memory cell of claim 1 wherein the programmed current is more than or equal to about 3×

10 5 amps.

20. The memory cell of claim 1 wherein the programmed current density is more than or equal to about 3.82×

10-3 amp/micron2.

21. The memory cell of claim 1 wherein the semiconductor material is not in contact with a silicide.