Current feedback method, current feedback circuit, driving circuit and switching power supply thereof

• US 9,246,384 B2
• Filed: 10/28/2014
• Issued: 01/26/2016
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Original Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd. (Silergy Corporation)
• Inventors: Liu, Guojia, Chen, Wei
• Primary Examiner(s): Dole, Timothy J
• Assistant Examiner(s): AHMED, YUSEF A
• Application Number:
  US14/525,974
• Publication Number:
  US 20150115922A1
• Time in Patent Office: 455 Days
• US Class Current: 1/1
• CPC Class Codes: G05F 3/26 Current mirrors
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation

Abstract

In one embodiment, a current feedback circuit can include: (i) a first current mirror circuit having an input terminal coupled to a source of a main power transistor of a switching power supply, and a control terminal configured to receive a PWM control signal, the first current mirror circuit being configured to generate a first mirror current; (ii) the first current mirror circuit and the main power transistor being on such that an output sampling current flows through the first current mirror circuit and the main power transistor when the PWM control signal is active; and (iii) a second current mirror circuit configured to generate an output feedback current that is in a predetermined direct proportion with the output sampling current, and is generated in accordance with the first mirror current.

Claims

1. A current feedback circuit, comprising:

a) a first current mirror circuit having an input terminal coupled to a source of a main power transistor of a switching power supply, and a control terminal configured to receive a pulse-width modulation (PWM) control signal, said first current mirror circuit being configured to generate a first mirror current;

b) said first current mirror circuit and said main power transistor being on such that an output sampling current flows through said first current mirror circuit and said main power transistor when said PWM control signal is active;

c) a second current mirror circuit configured to generate an output feedback current that is in a predetermined direct proportion with said output sampling current, and is generated in accordance with said first mirror current;

d) a current follower with input terminals coupled to a charging and discharging circuit and said first current mirror circuit, and an output terminal coupled to a current detection pin, wherein said current follower comprises an operational amplifier having input terminals coupled to input and output terminals of said first current mirror circuit, and a first transistor having a gate coupled to an output terminal of said operation amplifier, a source coupled to an inverting input terminal of said operational amplifier, and a drain coupled to said current detection pin; and

e) a first switch circuit coupled between said charging and discharging circuit and an input terminal of said operational amplifier, wherein said first switch circuit is off when said PWM control signal is inactive.

2. The current feedback circuit of claim 1, wherein said current feedback circuit is integrated into a chip comprising said current detection pin coupled to an output terminal of said first current mirror circuit.

3. The current feedback circuit of claim 2, wherein said first current mirror circuit is configured as a cascode current mirror with an input terminal coupled to said main power switch, and being configured to generate said first mirror current at said output terminal.

4. The current feedback circuit of claim 3, wherein said first current mirror circuit comprises:

a) second and third transistors having gates coupled to said PWM control signal, sources coupled to ground, wherein a drain of said second transistor is coupled to a source of said main power transistor, and a drain of said third transistor is coupled to said current detection pin; and

b) said second and third transistors and said main power transistor being on when said PWM control signal is active, wherein said output sampling current flows through said main power transistor and said second transistor, and said output feedback current flows through said third transistor and said current detection pin.

5. The current feedback circuit of claim 3, wherein said second current mirror is circuit coupled between said output terminal of said first current mirror circuit and said current detection pin, said second current mirror being configured to mirror said first mirror current to generate said output feedback current.

6. The current feedback circuit of claim 3, wherein:

a) said charging and discharging circuit is coupled to said gate and said source of said main power transistor;

b) said charging and discharging circuit is charged by a resonant current generated by an inductor of said switching power supply through a parasitic capacitor of said main power transistor when said main power transistor is turned off; and

c) said charging and discharging circuit is configured to provide a voltage supply to said current detection circuit when said main power transistor is on.

7. The current feedback circuit of claim 6, wherein said charging and discharging circuit comprises:

a) a diode having an anode coupled to said source of said main power transistor, and a cathode coupled to said gate of said main power transistor; and

b) a capacitor coupled to said gate of said main power transistor, and to ground.

8. The current feedback circuit of claim 7, wherein said current feedback circuit comprises a supply pin coupled between said capacitor and said diode.

9. The current feedback circuit of claim 1, further comprising a second switch circuit coupled between an input terminal of said operational amplifier and ground, wherein said second switch circuit is on when said PWM control signal is inactive.

10. The current feedback circuit of claim 9, wherein second switch circuit comprises:

a) an inverter is coupled between said PWM control signal and a gate of a fourth transistor; and

b) said fourth transistor having a drain coupled to a non-inverting input terminal of said operational amplifier, and a source coupled to ground.

11. The current feedback circuit of claim 1, further comprising a sampling resistor coupled to said current detection pin.

12. A driving circuit for a switching power supply, the driving circuit comprising:

a) the current feedback circuit of claim 1; and

b) a PWM control signal generation circuit configured to generate said PWM control in accordance with said output feedback current.

13. A switching power supply, comprising:

a) the driving circuit of claim 12; and

b) a power stage having said main power transistor, wherein said driving circuit is configured to drive said main power transistor in accordance with said PWM control signal to maintain said output current of said switching power supply as substantially constant.

14. A method of controlling a current feedback circuit, the method comprising:

a) receiving, by a first current mirror circuit, a pulse-width modulation (PWM) control signal;

b) turning on said first current mirror circuit and a main power transistor of a switching power supply such than an output sampling current flows through said first current mirror circuit and a source of said main power transistor when said PWM control signal is active;

c) generating, by a second current mirror circuit, an output feedback current in a predetermined direct proportion to said output sampling current; and

d) providing said output feedback current to a current detection pin;

e) wherein said current feedback circuit comprises a current follower with input terminals coupled to a charging and discharging circuit and said first current mirror circuit, and an output terminal coupled to a current detection pin, wherein said current follower comprises an operational amplifier having input terminals coupled to input and output terminals of said first current mirror circuit, and a first transistor having a gate coupled to an output terminal of said operation amplifier, a source coupled to an inverting input terminal of said operational amplifier, and a drain coupled to said current detection pin; and

f) wherein said current feedback circuit comprises a first switch circuit coupled between said charging and discharging circuit and an input terminal of said operational amplifier, wherein said first switch circuit is off when said PWM control signal is inactive.

15. The method of claim 14, wherein:

a) said first current mirror circuit and said main power transistor are off when said PWM control signal is inactive;

b) said charging and discharging circuit is charged by a resonant current from resonance between an inductor of said switching power supply and a parasitic capacitor of said main power transistor; and

c) said charging and discharging circuit is configured to provide a voltage supply to a gate of said main power transistor and a current detection circuit chip comprising said first current mirror circuit when said PWM control signal is active.

16. The method of claim 14, further comprising:

a) generating a first mirror current at an output terminal of said first mirror circuit; and

b) mirroring said first mirror current to generate said output feedback current.

17. The method of claim 14, further comprising:

a) following said first mirror current by said current follower; and

b) providing an output current of said current follower to said second current mirror circuit.