Digital phase lock loop circuit including finite impulse response filtering to reduce aliasing of quantization noise

• US 9,246,499 B2
• Filed: 05/21/2014
• Issued: 01/26/2016
• Est. Priority Date: 05/21/2014
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Balachandran, Ganesh K., Petkov, Vladimir P.
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US14/283,816
• Publication Number:
  US 20150341042A1
• Time in Patent Office: 615 Days
• Field of Search: 327/147, 327/156
• US Class Current: 1/1
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A digital phase lock loop circuit includes a phase detector, loop filter, finite impulse response filter (FIR), a plurality of digital to analog converters (DACs), a voltage controlled oscillator (VCO), and a divider. The FIR filter includes a predetermined number of taps, where each tap is connected to an input of one DAC in the plurality of DACs. The FIR filter attenuates high-frequency quantization error in a digital control signal that the plurality of DACs converts to an analog control signal for the VCO. The FIR filtered control signal reduces or eliminates quantization noise higher-frequency components that would otherwise be generated as DC quantization noise in a feedback signal generated by the divider.

Claims

1. A phase lock loop circuit comprising:

a phase detector having a first input that receives a reference signal with a predetermined waveform at a predetermined frequency and a second input that receives a feedback signal, the phase detector being configured to generate a digital control signal with reference to the reference signal and the feedback signal;

a loop filter having an input that receives the control signal from an output of the phase detector, the loop filter being configured to generate a digital filtered control signal;

a modulator having an input that receives the digital filtered control signal from an output of the loop filter, the modulator being configured to generate a dithered digital control signal with reference to the digital filtered control signal;

a finite impulse response (FIR) filter having a predetermined number of taps, an input that connects an output of the modulator to the predetermined number of taps, the FIR being configured to reduce quantization noise in the dithered digital control signal;

a plurality of DACs, each DAC having an input that is connected to an output of one of the taps in the FIR filter to generate an analog control signal in response to output from the FIR filter;

a voltage controlled oscillator (VCO) having an input connected to outputs of the plurality of DACs to receive the analog control signal from the plurality of DACs, the VCO being configured to generate an output signal having a frequency that corresponds to a multiple of the frequency of the reference signal with reference to the analog control signal;

a first divider having an input that receives the output signal from the VCO and an output that generates the feedback signal with reference to the output signal at the frequency of the reference signal for the second input of the phase detector; and

a second divider having an input connected to the output of the VCO and an output connected to each DAC in the plurality of DACs, the second divider being configured to generate a clock signal having a lower frequency than the frequency of the output signal and at least twice the frequency of the reference signal to control a sampling frequency in the plurality of DACs.

2. The phase lock loop circuit of claim 1, the predetermined number of taps in the FIR corresponding to a ratio of a first sampling frequency of the plurality of DACs to a second sampling frequency of the first divider, the first sampling frequency being greater than the second sampling frequency.

3. The phase lock loop circuit of claim 2, the predetermined number of taps in the FIR being thirty-two for the ratio of the first sampling frequency of the plurality of DACs to the second sampling frequency of the first divider of thirty-two to one.

4. The phase lock loop circuit of claim 2, the predetermined number of taps in the FIR being eight for the ratio of the first sampling frequency of the plurality of DACs to the second sampling frequency of the first divider of eight to one.

5. The phase lock loop circuit of claim 1 wherein the predetermined number of taps in the FIR filter produce a plurality of notches in a transfer function of the FIR filter, the plurality of notches being centered on at least a sampling frequency of the first divider and twice the sampling frequency of the first divider.

6. A phase lock loop circuit comprising:

a phase detector having a first input that receives a reference signal with a predetermined waveform at a predetermined frequency and a second input that receives a feedback signal, the phase detector being configured to generate a digital control signal in response to the reference signal and the feedback signal;

a loop filter having an input that receives the control signal from an output of the phase detector, the loop filter being configured to generate a digital filtered control signal;

a finite impulse response (FIR) filter having a predetermined number of taps and an input that is connected to an output of the loop filter, the FIR being configured to reduce quantization noise in the digital filtered control signal, wherein the predetermined number of taps in the FIR filter produce a plurality of notches in a transfer function of the FIR filter, the plurality of notches being centered on at least a sampling frequency of the divider and twice the sampling frequency of the divider;

a voltage controlled oscillator (VCO) having a plurality of tunable elements, each tunable element being connected to one tap in the plurality of taps in the FIR filter to enable the VCO to generate an output signal having a frequency that corresponds to a multiple of the frequency of the reference signal with reference to the digital filtered control signal; and

a divider having an input that receives the output signal from the VCO and an output that generates the feedback signal with reference to the output signal at the frequency of the reference signal for the second input of the phase detector.

7. The phase lock loop circuit of claim 6 further comprising:

a sigma-delta modulator having an output connected to the input of the FIR filter, the sigma-delta modulator being configured to generate a dither signal at a first frequency to dither the digital control signal; and

the predetermined number of taps in the FIR corresponding to a ratio of the first frequency of the dither signal to a second sampling frequency of the divider, the first frequency of the dither signal being greater than the second sampling frequency.

8. The phase lock loop circuit of claim 7, the predetermined number of taps in the FIR being three for the ratio of the first frequency of the dither signal to the second sampling frequency of the divider of three to one.