Vector signaling with reduced receiver complexity

• US 9,246,713 B2
• Filed: 06/24/2014
• Issued: 01/26/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Shokrollahi, Amin
• Primary Examiner(s): Flores, Leon
• Application Number:
  US14/313,966
• Publication Number:
  US 20140376668A1
• Time in Patent Office: 581 Days
• Field of Search: 375/316, 375/340, 375/341
• US Class Current: 1/1
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 17/18 Code selection mechanisms

Abstract

Methods and apparatuses are described to determine subsets of vector signaling codes capable of detection by smaller sets of comparators than required to detect the full code. The resulting lower receiver complexity allows systems utilizing such subset codes to be less complex and require less power.

Claims

1. A system including a receiver circuit, the receiver circuit comprising:

N conductors configured to receive a set of values corresponding to a sub-code, wherein N is greater than 2;

a sparse comparator circuit comprising strictly fewer than N*(N−

1)/2 graph-connected two-input comparators wherein each two-input comparator compares one of the values of the set of values received on one of the N conductors to another one of the values of the set of values received on some other one of the N conductors, wherein the sub-code comprises a maximum independent set of elements selected from a large code based on a graph comprising nodes representing the conductors and edges representing pairs of conductors being compared through at least one graph-connected two-input comparator, and wherein graph-connected two-input comparators comprise the graph being connected such that there are one or more edges connecting any pair of nodes; and

,

a decoder circuit to determine a data word based on N*(N−

1)/2 outputs of the circuit.

2. The system of claim 1 having six conductors, such that N=6, wherein the receiver circuit comprises:

three local comparator units having three fine-codeword comparator outputs;

an arithmetic unit connected to the six conductors, configured to generate a set of three coarse codeword element outputs; and

,

a non-sparse global comparator unit having three comparators connected to the set of three coarse codeword element outputs of the arithmetic unit, and configured to generate coarse codeword comparator outputs based on the coarse codeword element outputs.

3. The system of claim 1, further comprising a transmitter circuit, wherein the transmitter circuit comprises:

an encoder configured to encode a data word into a code word with N symbols; and

a set of drivers collectively configured to transmit output values corresponding to the code word.

4. A method of decoding symbols comprising:

receiving a set of symbols on a plurality of conductors;

determining n fine codeword comparator outputs using n local sparse comparator units, wherein n is an integer greater than 1 wherein the ith local comparator unit, where 1≦

i≦

n, compares an ith subset of N_i symbols that are elements of a corresponding fine codeword using strictly less than N_i*(N_i−

1)/2 graph-connected two-input comparators, where N_i is an integer greater than 1;

determining coarse codeword elements of a coarse codeword corresponding to the set of received symbols by forming arithmetic symbol combinations based on at least one subset of symbols;

determining coarse codeword comparator outputs based on the coarse codeword elements using a global comparator unit;

determining a data word based on the fine codeword comparator outputs and the coarse codeword comparator outputs.

5. The method of claim 4 wherein forming arithmetic symbol combinations comprises either averaging, summing, or subtracting the symbols of the subsets.

6. The method of claim 4 wherein determining coarse codeword comparator outputs based on the coarse codeword elements comprises:

forming intermediate codeword comparator outputs based on the coarse codeword elements using one or more intermediate comparator units having K inputs and providing fewer than K(K−

1)/2 comparator outputs;

determining higher-level coarse codeword elements of a higher-level coarse codeword corresponding to the set of received symbols by forming one or more arithmetic combinations of the coarse codeword elements;

determining higher-level coarse codeword comparator outputs based on the higher-level coarse codeword elements;

providing the coarse codeword comparator outputs as a set including the intermediate codeword comparator outputs and the higher-level coarse codeword comparator outputs.

7. The method of claim 6 wherein determining higher-level coarse codeword comparator outputs is also based directly on at least one coarse codeword element.

8. The method of claim 4 wherein determining a data word comprises converting the fine codeword comparator outputs and the coarse codeword comparator outputs to a data word using a decoder.

9. The method of claim 4 wherein determining a data word comprises using the fine codeword comparator outputs and the coarse codeword comparator outputs as the data word.

10. The method of claim 4 wherein the fine codeword elements are predetermined so that the sum of the fine codeword elements corresponds to a single element of a valid coarse codeword.

11. The method of claim 4, wherein each element of the fine codeword is selected from a set of at least three values.

12. An apparatus comprising:

a set of conductors configured to receive a set of symbols corresponding to a codeword;

an integer, n, of local sparse comparator units, wherein the ith local sparse comparator unit, where 1≦

i≦

n and n>

1, accepts at least N_i inputs representing elements of a fine codeword, the N_i inputs corresponding to an ith subset of the set of conductors, wherein each local sparse comparator unit comprises strictly less than N_i*(N_i−

1)/2 graph-connected two-input comparators where N_i is an integer greater than 1, the one or more local sparse comparator units having one or more fine codeword comparator outputs;

an arithmetic unit connected to a second subset of the set of conductors, and having coarse codeword element outputs at least one of which represents an arithmetic combination of signals on the second subset of the set of conductors; and

,

a global comparator unit connected to the coarse codeword element outputs and having coarse codeword comparator outputs based on the coarse codeword element outputs.

13. The apparatus of claim 12 further comprising a decoder connected to the one or more local comparator units and the global comparator unit for determining a data word based on the fine codeword comparator outputs and the coarse codeword comparator outputs.

14. The apparatus of claim 12 wherein the arithmetic unit is configured to form arithmetic symbol combinations by either averaging, summing, or subtracting combinations of the signals on the second subset of the N conductors.

15. The apparatus of claim 12 wherein the global comparator unit comprises a second arithmetic unit and additional comparators.

16. An apparatus comprising:

six conductors;

a sparse comparator unit having six inputs connected to the six conductors, and having three local sparse comparator units having three fine-codeword comparator outputs, wherein each local sparse comparator unit comprises one graph-connected two-input comparator;

an arithmetic unit connected to the six conductors, and having three averaging units, each averaging unit generating a coarse codeword element output; and

,

a non-sparse global comparator unit having three two-input comparators connected to the coarse codeword element outputs of the arithmetic unit, and having coarse codeword comparator outputs based on the coarse codeword element outputs.

17. The apparatus of claim 16 further comprising a decoder connected to the sparse comparator unit and the non-sparse global comparator unit, the decoder configured to generate a data word.

18. The apparatus of claim 16, wherein generating a data word comprises using the three fine-codeword comparator outputs and the coarse codeword comparator outputs as the data word.

19. The apparatus of claim 16, wherein the arithmetic unit is configured to generate the coarse codeword element outputs by either averaging, summing, or subtracting combinations of the six inputs of the six conductors.

20. The apparatus of claim 16, wherein the non-sparse global comparator unit comprises a second arithmetic unit and additional two-input comparators.