Method of generating and receiving packets in low energy critical infrastructure monitoring system

• US 9,246,725 B2
• Filed: 09/06/2012
• Issued: 01/26/2016
• Est. Priority Date: 09/06/2011
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Oh, Mi Kyung, Jeon, Young Ae, Lee, Sangjae, Kim, Jaehwan, Shin, Cheol-ho, Kim, Byoung Hak, Lee, Seung Sik, Choi, Sangsung, Kim, Jae Young
• Primary Examiner(s): Patel, Parth
• Application Number:
  US13/605,230
• Publication Number:
  US 20130058360A1
• Time in Patent Office: 1,237 Days
• Field of Search: 370/537, 370/338, 370/206, 370/447, 370/468, 370/503, 370/442, 370/474, 370/273, 370/208, 370/337, 370/445, 370/315, 375/341, 375/261, 375/272, 375/303, 375/365, 375/141, 375/267, 375/144, 375/150, 375/259, 375/279, 375/239, 375/269, 375/295, 375/224, 375/273
• US Class Current: 1/1
• CPC Class Codes: H04L 1/0009 by adapting the channel coding H04L1/1812 takes precedence
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 1/007 Unequal error protection for format H04L1/0078; for codes per se H03M13/35
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 27/12 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits

Abstract

A method of generating a packet for low energy critical infrastructure monitoring (LECIM) wireless communication is provided. The method includes steps of generating a first bit string by multiplexing a physical layer header (PHR) bit and a physical layer service data unit (PSDU) bit; convolution encoding the first bit string; interleaving the convolution-encoded first bit string; generating a second bit string by multiplexing the interleaved first bit string with a synchronization header (SHR) bit; and modulating the second bit string with a frequency shift keying (FSK) method and a position-based FSK method.

Claims

1. A method of modulation, the method comprising:

mapping each bit of a bit string to at least four symbols;

allocating a modulation frequency to each of the symbols;

allocating a position to be transmitted in a duration of each of the symbols; and

modulating each of the symbols based on the modulation frequency and the position,

wherein the allocating comprises dividing the duration of the symbol into a plurality of positions and selecting a position at which the allocated modulation frequency is to be transmitted and a position at which the allocated modulation frequency is not to be transmitted.

2. The method of claim 1, wherein the mapping of the bit string comprises

dividing the bit string into 00, 01, 10, and 11, and the allocating of the modulation frequency comprises

allocating a first modulation frequency to the 00 and 01;

and

allocating a second modulation frequency different from the first modulation frequency to the 10 and 11.

3. The method of claim 2, wherein the allocating of the position comprises

allocating a first position of the duration to the 00 and 10;

and

allocating a second position different from the first position of the duration to the 01 and 11.

4. A method of generating a packet, the method comprising:

generating a first bit string by multiplexing a physical layer header (PHR) bit and a physical layer service data unit (PSDU) bit with synchronization header (SHR) bits; and

modulating the first bit string with at least one of a frequency shift keying (FSK) method and a method in which position information is reflected to the FSK method,

wherein each of symbols in the first bit string is modulated based on modulation frequency and position that are allocated to the each of the symbols,

wherein, when the position is allocated to the each of the symbols, the duration of the symbol is divided into a plurality of positions, and a position at which the allocated modulation frequency is to be transmitted and a position at which the allocated modulation frequency is not to be transmitted are selected.

5. The method of claim 4, wherein the PHR bit comprises at least one parity check bit which is generated by combination of the bits which are included in the PHR.

6. The method of claim 4, further comprising

encoding the PHR bit and the PSDU bit,

wherein the generating of the first bit string comprises multiplexing the encoded PHR bit and the encoded PSDU bit with the SHR bit.

7. The method of claim 6, further comprising

interleaving the encoded PHR bit and the encoded PSDU bit,

wherein the generating of the first bit string comprises multiplexing the interleaved PHR bit and the interleaved PSDU bit with the SHR bit.

8. The method of claim 7, wherein the interleaving the encoded PHR bit and the encoded PSDU bit comprises

applying a first length of interleaving to the encoded PHR bit;

and

applying a second length of interleaving to the encoded PSDU bit, wherein the second length of interleaving is different from the first length of interleaving.

9. The method of claim 7, further comprising

data-whitening the interleaved PSDU bit,

wherein the generating of the first bit string comprises multiplexing the interleaved PHR bit and the data-whitened PSDU bit with the SHR bit.

10. The method of claim 9, further comprising

applying spreading code to the interleaved PHR bit and the data whitened PSDU bit,

wherein the generating of the first bit string comprises multiplexing the spread PHR bit and the spread PSDU bit with the SHR bit.

11. The method of claim 10, wherein the spreading code has a pattern in which “

01”

or “

10”

is repeated.

12. The method of claim 4, wherein a second bit string of the first bit string comprises a bit string of the SHR bit, and

a third bit string different from the second bit string of the first bit string comprises a bit string of the PHR bit and a bit string of the PSDU bit.

13. The method of claim 12, wherein a preamble has a pattern in which 0 and 1 are alternately repeated, wherein the SFD is generated by a predetermined sequence configured by “

0” and

“

1”

or a combination of the predetermined sequence.

14. The method of claim 4, wherein a second bit string of the first bit string comprises a bit string of the SHR bit and a bit string of the PHR bit, and

a third bit string different from the second bit string of the first bit string comprises a bit string of the PSDU bit.

15. The method of claim 4, further comprising repeatedly transmitting a portion of the modulated first bit string by a predetermined number of times.

16. The method of claim 4, wherein the PSDU bit comprises a cyclic redundancy checking (CRC) bit.

17. The method of claim 4, wherein the SHR bit comprises a preamble;

and

a start frame delimiter (SFD) which is comprised of at least one sequence selected from a predetermined SFD sequence group and repeated a predetermined number of times.

18. The method of claim 4, wherein the modulating of the first bit string comprises

mapping each bit of the first bit string to at least four symbols;

allocating a modulation frequency to each of the symbols

allocating a position to be transmitted in a duration of each of the symbols; and

modulating each of the symbols based on the modulation frequency and the position.

19. A method of receiving a packet in a receiver, the method comprising:

demodulating a packet that is received from an antenna with at least one of a frequency shift keying (FSK) method and a method in which position information is reflected to the FSK method;

de-interleaving the demodulated packet;

decoding the de-interleaved packet; and

demultiplexing the decoded packet to a physical layer header (PHR) bit and a physical layer service data unit (PSDU) bit,

wherein each of symbols in the received packet is modulated based on modulation frequency and position that are allocated to the each of the symbols,

wherein, when the position is allocated to the each of the symbols, the duration of the symbol is divided into a plurality of positions, and a position at which the allocated modulation frequency is to be transmitted and a position at which the allocated modulation frequency is not to be transmitted are selected.

20. The method of claim 19, wherein the decoding of the de-interleaved packet comprises

decoding the de-interleaved packet using soft decision viterbi algorithm by a coordinator of a sensor network when the receiver is included in the coordinator of the sensor network;

and

decoding the de-interleaved packet using hard decision viterbi algorithm by an endpoint device of a sensor network when the receiver is included in the endpoint device of the sensor network.