Video encoding and video/audio/data multiplexing device

• US 9,247,263 B2
• Filed: 06/14/2006
• Issued: 01/26/2016
• Est. Priority Date: 04/06/1999
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Yavits, Leonid, Morad, Amir
• Primary Examiner(s): VO, TUNG T
• Application Number:
  US11/452,480
• Publication Number:
  US 20060233261A1
• Time in Patent Office: 3,513 Days
• Field of Search: 348/480, 348/721, 348/700, 375/240.18, 375/240.16, 375/240.12, 375/240.01, 375/240.24, 370/394, 370/535, 345/473
• US Class Current: 1/1
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/43 Hardware specially adapted for motion estimation or compensation
• CPC Class Codes: H04N 19/436 using parallelised computational arrangements
• CPC Class Codes: H04N 19/61 in combination with predictive coding

Abstract

The present invention provides a buffer architecture and latency reduction mechanism for buffering uncompressed/compressed information. This combination provides for a proficient division of the encoding task and quicker through-put time. The invention teaches a single chip digital signal processing device for real time video/audio compression comprising a plurality of processors, including a video input processor, a motion estimation processor, a digital signal processor, and a bitstream processor, wherein processing and transfer of the signals within the device is done in a macroblock-by-macroblock manner. The device can include a multiplexing processor that is comprised of a storage unit which buffers a compressed video bitstream and a processor which retrieves the compressed video bitstream from the storage unit and produces a multiplexed data stream whereby the compressed video bitstream is processed in a pipeline manner.

Claims

1. A multiplexing processor comprising:

a first video storage unit operable to accumulate compressed video data received from a bitstream processor at a first real time rate, and transfer the accumulated compressed video data to an external memory unit at a first burst rate, by adjusting the first real time rate to an external communication rate of the external memory unit;

a second video storage unit operable to receive compressed video data from the external memory unit at a second burst rate, and transfer the received compressed video data to a video processor at a second real time rate, by adjusting the second burst rate to an internal communication rate of the multiplexing processor;

the external memory unit comprising

a first buffer operable to receive the compressed video data from said first storage unit at the first burst rate, and

a second buffer operable to retrieve the compressed video data from said first buffer, and transfer the retrieved data to the second video storage unit at the second burst rate, thereby allowing a difference between the first burst rate and the second burst rate; and

a video processor operable to retrieve the compressed video data from said second buffer via the second video storage unit at the second real time rate.

2. The multiplexing processor according to claim 1, wherein the first burst rate is the external memory communication rate.

3. The multiplexing processor according to claim 1, wherein said external memory unit acts as a temporary video buffer, accumulating video data when said video processor is unable to accept said video data.

4. The multiplexing processor according to claim 1, further comprising a memory controller operable to control data communication with the video processor.

5. The multiplexing processor according to claim 1, wherein compressed video data is transferred in a macroblock-by-macroblock manner.

6. The multiplexing processor of claim 1, wherein the memory unit further comprises a third buffer operable to retrieve audio or user data at a third, burst data rate.

7. The multiplexing processor of claim 6, wherein the video processor is further operable to retrieve the audio or user data from the third buffer at the second rate, and multiplex the retrieved compressed video data and retrieved audio or user data into an output stream.

8. The multiplexing processor of claim 7, wherein the memory unit further comprises a fourth buffer operable to receive the multiplexed output stream at the second rate, and transmit the multiplexed output stream at a fourth, burst data rate.

9. The multiplexing processor of claim 1,

wherein the first buffer is further operable to provide the video data to a second memory unit at a third, burst rate;

wherein the second buffer is operable to retrieve the video data from the first buffer via the second memory unit; and

wherein the second memory unit is operable to store the pipelined video data responsive to an external receiving device being unable to accept processed video data from the video processor.

10. The multiplexing processor of claim 1, wherein the external memory unit is dynamically allocated, responsive to the video processor being unable to accept the compressed video from the bitstream processor.

11. The multiplexing processor of claim 10, wherein the external memory unit has a greater storage size than the first video storage unit or second video storage unit.

12. A multiplexing processor comprising:

a first storage unit operable to accumulate data received from a first processor at a first real time data rate, and transfer the accumulated data to an external memory unit at a first burst rate by adjusting the data rate to an external communication rate of the external memory unit;

a second storage unit operable to receive data from the external memory unit at a second burst data rate, and transfer the received data to a second processor at a second real time rate lay adjusting the data rate to an internal communication rate of the multiplexing processor;

a memory controller operable to transfer said data between said first and second storage units and an external memory unit;

the external memory unit comprising

a first buffer operable to receive the data from said first storage unit at the first burst rate, and

a second buffer operable to retrieve the data from said first buffer and transfer the retrieved data to the second storage unit at the second burst rate, thereby allowing a difference between the first burst rate and the second burst rate; and

a co-processor operable to retrieve the data from said second buffer via the second storage unit at the second real time rate.

13. The multiplexing processor according to claim 12, wherein the first burst rate is the external memory communication rate.

14. The multiplexing processor according to claim 12, wherein said external memory unit acts as a temporary buffer, accumulating data when said co-processor is unable to accept said data.

15. The multiplexing processor of claim 12, wherein the external memory unit is dynamically allocated, responsive to the co-processor being unable to accept the data from the first processor.

16. The multiplexing processor of claim 15, wherein the external memory unit has a greater storage size than the first video storage unit or second video storage unit.