High quality factor inductor and high quality factor filter in package substrate or printed circuit board (PCB)

• US 9,247,647 B1
• Filed: 09/11/2014
• Issued: 01/26/2016
• Est. Priority Date: 09/11/2014
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yoon, Jung Ho, Zhang, Xiaonan, Lee, Jong-Hoon, Song, Young Kyu, Jow, Uei-Ming
• Primary Examiner(s): Nhu, David
• Application Number:
  US14/484,000
• Time in Patent Office: 502 Days
• Field of Search: 257/531, 257/277, 257/678, 257/528, 257/532, 257/533, 257/681, 257/734, 257/737, 257/758, 257/E21.006, 257/E21.007, 257/E21.008, 257/E21.264, 257/E21.267, 257/E21.327, 257/E21.508, 257/E21.509, 257/E21.499
• US Class Current: 1/1
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/116 Lands, clearance holes or other lay-out details concerning the surrounding of a via
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/094 : Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/09672 : Superposed layout, i.e. in different planes
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/4007 : Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/4688 : Composite multilayer circuits, i.e. comprising insulating layers having different properties having a special base or central core H05K3/4602

Abstract

A package substrate (or printed circuit board) that includes at least one dielectric layer, a first inductor structure is at least partially located in the dielectric layer, a third interconnect, and a second inductor structure. The first inductor structure includes a first interconnect, a first via coupled to the first interconnect, and a second interconnect coupled to the first via. The third interconnect is coupled to the first inductor structure. The third interconnect is configured to provide an electrical path for a ground signal. The second inductor structure is at least partially located in the dielectric layer. The second inductor is coupled to the third interconnect. The second inductor structure includes a fourth interconnect, a second via coupled to the fourth interconnect, and a fifth interconnect coupled to the second via. The first and second inductor structures are configured to operate with a capacitor as a 3^rd harmonic suppression filter.

Claims

1. A package substrate comprising:

at least one dielectric layer;

a first inductor structure at least partially located in the dielectric layer, the first inductor structure comprising;

a first interconnect;

a first via coupled to the first interconnect; and

a second interconnect coupled to the first via;

a third interconnect coupled to the first inductor structure, the third interconnect configured to provide an electrical path for a ground signal; and

a second inductor structure at least partially located in the dielectric layer, the second inductor coupled to the third interconnect, the second inductor structure comprising;

a fourth interconnect;

a second via coupled to the fourth interconnect; and

a fifth interconnect coupled to the second via.

2. The package substrate of claim 1, wherein the first inductor structure and the second inductor structure are inductor structures from a plurality of inductor structures in the package substrate, the plurality of inductor structures arranged in an array configuration.

3. The package substrate of claim 1, wherein the first inductor structure includes a first solder ball.

4. The package substrate of claim 1, wherein the first and second inductor structures are configured to operate with a capacitor as a filter.

5. The package substrate of claim 4, wherein the filter is one of at least a suppression filter, and/or a 3^rd harmonic suppression filter.

6. The package substrate of claim 4, wherein the capacitor is located in an integrated device that is coupled to the package substrate.

7. The package substrate of claim 1, wherein the third interconnect is part of the second interconnect and the fifth interconnect.

8. The package substrate of claim 1, wherein the first inductor structure and the second inductor structure, individually or collectively, comprises a quality factor of about 20 or more.

9. The package substrate of claim 1, wherein the first inductor structure and the second inductor structure, individually or collectively, comprises a quality factor of about 200 or more.

10. The package substrate of claim 1, wherein the package substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

11. A package substrate comprising:

at least one dielectric layer;

a first inductive means configured to provide inductance in the package substrate;

an interconnect means coupled to the first inductive means, the interconnect means configured to provide an electrical path for a ground signal; and

a second inductive means configured to provide inductance in the package substrate, the second inductive means coupled to the interconnect means;

wherein the first and second inductive means are configured to operate with a capacitive means as a filter.

12. The package substrate of claim 11, wherein the first inductive means and the second inductive means are inductive means from a plurality of inductor means in the package substrate, the plurality of inductive means arranged in an array configuration.

13. The package substrate of claim 11, wherein the filter is one of at least a suppression filter, and/or a 3^rd harmonic suppression filter.

14. The package substrate of claim 11, wherein the package substrate is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

15. A printed circuit board (PCB) comprising:

at least one dielectric layer;

a first inductor structure at least partially located in the dielectric layer, the first inductor structure comprising;

a first interconnect;

a first via coupled to the first interconnect; and

a second interconnect coupled to the first via;

a third interconnect coupled to the first inductor structure, the third interconnect configured to provide an electrical path for a ground signal; and

a second inductor structure at least partially located in the dielectric layer, the second inductor coupled to the third interconnect, the second inductor structure comprising;

a fourth interconnect;

a second via coupled to the fourth interconnect; and

a fifth interconnect coupled to the second via.

16. The printed circuit board of claim 15, wherein the first inductor structure and the second inductor structure are inductor structures from a plurality of inductor structures in the printed circuit board (PCB), wherein the plurality of inductor structures are arranged in an array configuration.

17. The printed circuit board of claim 15, wherein the first inductor structure includes a first solder ball.

18. The printed circuit board of claim 15, wherein the first and second inductor structures are configured to operate with a capacitor as a filter.

19. The printed circuit board of claim 18, wherein the filter is one of at least a suppression filter, and/or a 3^rd harmonic suppression filter.

20. The printed circuit board of claim 18, wherein the capacitor is located in an integrated device that is coupled to the printed circuit board (PCB).

21. The printed circuit board of claim 15, wherein the third interconnect is part of the second interconnect and the fifth interconnect.

22. The printed circuit board of claim 15, wherein the first inductor structure and the second inductor structure, individually or collectively, comprises a quality factor of about 20 or more.

23. The printed circuit board of claim 15, wherein the first inductor structure and the second inductor structure, individually or collectively, comprises a quality factor of about 200 or more.

24. The printed circuit board of claim 15, wherein the printed circuit board is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.

25. A printed circuit board comprising:

at least one dielectric layer;

a first inductive means configured to provide inductance in the printed circuit board (PCB);

an interconnect means coupled to the first inductive means, the interconnect means configured to provide an electrical path for a ground signal; and

a second inductive means configured to provide inductance in the printed circuit board (PCB), the second inductive means coupled to the interconnect means;

wherein the first and second inductive means are configured to operate with a capacitive means as a filter.

26. The printed circuit board of claim 25, wherein the first inductive means and the second inductive means are inductive means from a plurality of inductor means in the printed circuit board (PCB), wherein the plurality of inductive means are arranged in an array configuration.

27. The printed circuit board of claim 25, wherein the filter is one of at least a suppression filter, and/or a 3^rd harmonic suppression filter.

28. The printed circuit board of claim 25, wherein the printed circuit board is incorporated into at least one of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, and/or a laptop computer.