Electro-polishing and porosification

• US 9,249,523 B2
• Filed: 09/27/2013
• Issued: 02/02/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Maxeon Solar Pte Limited
• Original Assignee: Sunpower Corporation (Totalenergies Se)
• Inventors: Rim, Seung Bum
• Primary Examiner(s): Smith, Nicholas A
• Application Number:
  US14/039,597
• Publication Number:
  US 20150090605A1
• Time in Patent Office: 858 Days
• Field of Search: 205/646, 205/665
• US Class Current: 1/1
• CPC Class Codes: C25F 3/12 of semiconducting materials
• CPC Class Codes: C25F 3/30 of semiconducting materials
• CPC Class Codes: C25F 7/00 Constructional parts, or assemblies thereof, of cells for electrolytic removal of material from objects for both electrolytic coating and removal C25D; Servicing or operating
• CPC Class Codes: H01L 21/0201 Specific process step
• CPC Class Codes: H01L 21/0203 Making porous regions on the surface
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 31/0682 back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells
• CPC Class Codes: Y02E 10/548 Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Forming a porous layer on a silicon substrate is disclosed. Forming the porous layer can include placing a silicon substrate in a first solution and conducting a first current through the silicon substrate. It can further include conducting a second current through the silicon substrate resulting in a porous layer on the silicon substrate.

Claims

1. A method, comprising:

placing a silicon substrate in a first solution;

conducting a first current through the silicon substrate in the first solution; and

conducting a second current through the silicon substrate resulting in a porous layer on the silicon substrate, wherein conducting the first current comprises conducting the first current with a current density of 1-100 mA/cm², resulting in a polished layer on the silicon substrate, wherein the first current flattens a surface of the silicon substrate; and

conducting the second current comprises conducting the second current with a current density of 0.1-50 mA/cm², resulting in a porous layer on the polished layer on the silicon substrate.

2. The method of claim 1, wherein conducting the first current comprises applying a high bias voltage.

3. The method of claim 1, wherein conducting the second current comprises applying a low bias voltage.

4. The method of claim 1, wherein conducting the first current results in electro-polishing the silicon substrate.

5. The method of claim 1, wherein conducting the first current comprises conducting the first current that is based on a size of the silicon substrate.

6. The method of claim 1, wherein conducting the first current comprises conducting the first current that is based on a concentration of the solution.

7. The method of claim 1, wherein conducting the second current comprises conducting the second current that is based on a size of the silicon substrate.

8. The method of claim 1, wherein conducting the second current comprises conducting the second current that is based on a concentration of the solution.

9. The method of claim 1, wherein placing the silicon substrate in the first or second solution comprises placing the silicon substrate in a solution comprised of a chemical selected from the group consisting of hydrofluoric acid (HF), isopropyl alcohol (IPA) and ethanol.

10. The method of claim 1, wherein conducting the second current through the silicon substrate comprises conducting the second current through the silicon substrate in a second solution.

11. The method of claim 10, wherein conducting the second current through the silicon substrate in the second solution comprises conducting the second current through the silicon substrate in a porosification solution.

12. A method for forming a porous layer on a silicon substrate, the method comprising:

placing a silicon substrate in a first solution;

applying a high bias voltage through the silicon substrate, resulting in a polished layer on the silicon substrate, wherein the high bias voltage flattens a surface of the silicon substrate;

placing a silicon substrate in a second solution; and

forming a porous layer on the polished layer, wherein forming the porous layer includes applying a low bias voltage through the silicon substrate.

13. The method of claim 12, wherein placing the silicon substrate in the first solution comprises placing the silicon substrate in an electro-polishing solution.

14. The method of claim 12, wherein placing the silicon substrate in the second solution comprises placing the silicon substrate in a porosification solution.

15. The method of claim 12, wherein placing the silicon substrate in the first or second solution comprises placing the silicon substrate in a solution comprised of a chemical selected from the group consisting of hydrofluoric acid (HF), isopropyl alcohol (IPA) and ethanol.

16. A method for forming a porous layer on a silicon substrate, the method comprising:

placing a silicon substrate in an electro-polishing solution;

electro-polishing the silicon substrate, wherein electro-polishing includes conducting a first current through the silicon substrate, resulting in a polished layer on the silicon substrate, wherein the first current flattens a surface of the silicon substrate;

placing the silicon substrate in a porosification solution; and

forming a porous layer on the polished layer, wherein forming the porous layer includes conducting a second current through the silicon substrate.

17. The method of claim 16, wherein conducting the first current comprises applying a high bias voltage.

18. The method of claim 16, wherein conducting the second current comprises applying a low bias voltage.

19. The method of claim 16, wherein placing the silicon substrate in the electro-polishing or porosification solution comprises placing the silicon substrate in a solution comprised of a chemical selected from the group consisting of hydrofluoric acid (HF), isopropyl alcohol (IPA) and ethanol.