Wafer-level testing method for singulated 3D-stacked chip cubes

• US 9,250,288 B2
• Filed: 09/05/2013
• Issued: 02/02/2016
• Est. Priority Date: 09/05/2013
• Status: Active Grant

• Current Assignee: Powertech Technology Inc
• Original Assignee: Powertech Technology Inc
• Inventors: Chan, Kun-Chih, Chen, Shin-Kung, Lin, Sheng-Chi
• Primary Examiner(s): Koval, Melissa
• Assistant Examiner(s): MCDONNOUGH, COURTNEY G
• Application Number:
  US14/018,697
• Publication Number:
  US 20150061718A1
• Time in Patent Office: 880 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues.

Claims

1. A wafer-level testing method for testing a plurality of singulated 3D-stacked chip cubes comprising the steps of:

providing a carrier wafer with the same dimension as a semiconductor wafer for loading in a wafer tester;

attaching a plurality of first 3D-stacked chip cubes onto the carrier wafer according to a first wafer map, wherein the first wafer map defines a plurality of first probe card activated regions, each being corresponding to a probe card in the wafer tester and including a plurality of first component-attaching regions to constitute a M-by-N matrix, wherein each first component-attaching region is one-to-one corresponding to one of the first 3D-stacked chip cubes on the carrier wafer and is one-to-one corresponding to one of a plurality of component probing units of the probe card;

proceeding a first wafer-level testing in the wafer tester, including probing the first 3D-stacked chip cubes disposed in each corresponding first probe card activated region by the probe card whereas the electrical functions of the component probing units of the probe card are fully activated;

building a second wafer map according to the testing results of the first wafer-level testing to confirm one or more prone-to-overkill component-attaching regions in each first probe card activated region, wherein the second wafer map defines a plurality of second probe card activated regions, each being corresponding to the probe card and including a plurality of second component-attaching regions arranged in a same pattern to constitute an incomplete matrix by excluding the above mentioned prone-to-overkill component-attaching regions;

attaching a plurality of second 3D-stacked chip cubes with the same dimension as the first 3D-stacked chip cubes on the carrier wafer according to the second wafer map whereas the second 3D-stacked chip cubes are not disposed in the corresponding prone-to-overkill component-attaching regions; and

proceeding a second wafer-level testing in the wafer tester, including probing the second 3D-stacked chip cubes in each corresponding second probe card activated region by the probe card.

2. The wafer-level testing method as claimed in claim 1, wherein the electrical functions of the component probing units of the probe card are partially activated and the electrical functions of one or more of the component probing units corresponding to the above mentioned prone-to-overkill component-attaching regions are deactivated during the second wafer-level testing step.

3. The wafer-level testing method as claimed in claim 1, wherein at least one row of first non-probing regions are reserved between the first probe card activated regions according to the first wafer map, wherein the unit dimension of the first non-probing regions has the same dimension as the unit dimension of the first component-attaching regions.

4. The wafer-level testing method as claimed in claim 3, wherein at least one row of second non-probing regions are reserved between the second probe card activated regions according to the second wafer map, wherein the unit dimension of the second non-probing regions has the same dimension as the unit dimension of the second component-attaching regions.

5. The wafer-level testing method as claimed in claim 1, wherein each first 3D-stacked chip cube consists of a plurality of known good dice and each second 3D-stacked chip cube consists of a plurality of untested dice.