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Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network

  • US 9,250,900 B1
  • Filed: 10/01/2014
  • Issued: 02/02/2016
  • Est. Priority Date: 10/01/2014
  • Status: Active Grant
First Claim
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1. A computer implemented method for implementing a microprocessor with a selective register file bypass network, comprising:

  • removing late bypasses from a register file bypass network of a microprocessor design;

    automatically adding one or more late bypasses, which are a smaller subset of the late bypasses removed, to the register file bypass network based in part upon analysis results of a plurality of instructions to be executed by the microprocessor; and

    generating an electronic design for at least the register file bypass network with the one or more late bypasses that are automatically added to the register file bypass network to reduce an area on silicon occupied by the electronic design or to improve performance of the microprocessor design.

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