Method, system, and computer program product for implementing a microprocessor with a customizable register file bypass network

• US 9,250,900 B1
• Filed: 10/01/2014
• Issued: 02/02/2016
• Est. Priority Date: 10/01/2014
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Sun, Fei, Kim, James Sangkyu, Tsukamoto, Kyle Satoshi
• Primary Examiner(s): Ngo, Brian
• Application Number:
  US14/503,410
• Time in Patent Office: 489 Days
• Field of Search: 716/100, 716/104, 716/106, 716/108, 716/132, 712/214, 712/217
• US Class Current: 1/1
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

Methods and systems for implementing a microprocessor with a selective register file bypass network are disclosed. Late bypasses are removed from a register file bypass network of a microprocessor design. One or more late bypasses are then added back to the register file bypass network based at least in part upon the results of analyzing a plurality of instructions that are to be processed in an instruction pipeline of the microprocessor. An electronic design for at least the register file bypass network is then generated with these one or more late bypasses that are added to the register file bypass network. Without incurring additional hardware or cost for the microprocessor design, one or more bypasses in the register file bypass network may be optionally shared among multiple free-riders, and an entire port stage may also be optionally bypassed to another port stage based upon one or more criteria.

Claims

1. A computer implemented method for implementing a microprocessor with a selective register file bypass network, comprising:

removing late bypasses from a register file bypass network of a microprocessor design;

automatically adding one or more late bypasses, which are a smaller subset of the late bypasses removed, to the register file bypass network based in part upon analysis results of a plurality of instructions to be executed by the microprocessor; and

generating an electronic design for at least the register file bypass network with the one or more late bypasses that are automatically added to the register file bypass network to reduce an area on silicon occupied by the electronic design or to improve performance of the microprocessor design.

2. The computer implemented method of claim 1, further comprising:

automatically adding one or more early bypasses to the electronic design;

automatically transmitting information that includes the one or more early bypasses and indicates that the electronic design includes no late bypasses by using a register file specification from a compiler to a register file generation module;

automatically adding stall logic in response to the information indicating that the electronic design includes no late bypasses; and

automatically generating or modifying the electronic design to include no bypasses by using at least the information with the register file generation module.

3. The computer implemented method of claim 2, further comprising:

adding a first cycle or relaxing timing requirements for a removed late bypass route by converting the removed bypass route to at least a first instruction pipeline stage to an early bypass of a second instruction pipeline stage, wherein

the first instruction pipeline stage precedes the second instruction pipeline stage.

4. The computer implemented method of claim 3, further comprising:

adding a second cycle to one or more output operands of at least some of the plurality of instructions, wherein

the one or more output operands correspond to one or more late bypasses of the late bypasses that have been removed.

5. The computer implemented method of claim 1, further comprising:

identifying a first granularity level for specifying the one or more late bypasses; and

sharing a first bypass specification for specifying a first bypass of the one or more late bypasses with at least another bypass, wherein the one or more late bypasses comprise multiple late bypasses that include the at least another bypass.

6. The computer implemented method of claim 5, further comprising:

determining a plurality of requirements for a first port stage of a register file of the microprocessor based at least in part upon the first bypass specification, wherein the first port stage includes a write port stage;

elaborating the first bypass specification at the first granularity level to include information of one or more slot indices; and

mapping one or more operands to one or more ports of the register file.

7. The computer implemented method of claim 6, further comprising:

for a first bypass in the first bypass specification, connecting a first operation operand, negation of an operation output kill, and an opcode decode to respective signal sources;

determining whether or not a first operation argument is bypassed to a second operation argument in one bypass of the one or more late bypasses to generate determination results; and

modifying the electronic design based at least in part upon the determination results.

8. The computer implemented method of claim 1, further comprising:

sharing at least one bypass of the one or more late bypasses among a plurality of free-riders.

9. The computer implemented method of claim 8, further comprising:

identifying a first set of instructions in a semantic from the plurality of instructions in a slot index that writes to output operands; and

associating the first set of instructions with a control signal while reusing the output operands and same enable signals for the some instructions.

10. The computer implemented method of claim 8, further comprising:

identifying a second set of instructions that read from a first port stage;

bypassing the second set of instructions to a first operand in the first port stage by using a first bypass of the one or more late bypasses that are automatically added to the register file bypass network; and

sharing the first bypass with one or more other operands in the first port stage by indicating information about the first bypass to the one or more other operands in the first port stage.

11. The computer implemented method of claim 8, further comprising:

determining whether a first set of instructions in a semantic or a second set of instructions that read from a first port stage benefits from the at least one bypass to generate determination results; and

determining whether or not the at least one bypass is software-visible based at least in part upon the determination results.

12. The computer implemented method of claim 1, further comprising:

bypassing a first port stage in the instruction pipeline of the microprocessor to a second port stage by using at least one bypass of the one or more late bypasses.

13. The computer implemented method of claim 12, further comprising:

identifying a first port bypass in the one or more late bypasses from the first port stage to the second port stage;

identifying write port data and multiple signals for the first port stage; and

transmitting information or data concerning the first port bypass to a register file generation module.

14. The computer implemented method of claim 12, further comprising:

converting the first port bypass into an operand bypass that bypasses a first operand to a second operand; and

transmitting information concerning the operand bypass to one or more software tools for the one or more software tools to perform their respective functions.

15. The computer implemented method of claim 12, further comprising:

determining whether a set of instructions benefits from the first port bypass to generate determination results; and

determining whether or not the first port bypass is visible by the one or more software tools based at least in part upon the determination results.

16. A system for implementing a microprocessor with a selective register file bypass network, comprising:

a processor or a processor core executing one or more threads of execution of a computing system;

non-transitory computer accessible storage medium holding program code that includes a sequence of instructions that, when executed by the processor or processor core, cause the processor or processor core to at least remove late bypasses from a register file bypass network of a microprocessor design, automatically add one or more late bypasses, which are a smaller subset of the late bypasses removed, to the register file bypass network based at least in part upon analysis results of a plurality of instructions to be processed in an instruction pipeline of the microprocessor, and generate an electronic design for at least the register file bypass network with the one or more late bypasses that are automatically added to the register file bypass network to reduce an area on silicon occupied by the electronic design or to improve performance of the microprocessor design.

17. The system of claim 16, wherein the non-transitory memory holds the program code, and the program code includes further instructions that, when executed by the processor or processor core, cause the processor or processor core to share at least one bypass of the one or more late bypasses among a plurality of free-riders.

18. The system of claim 16, wherein the non-transitory memory holds the program code, and the program code includes further instructions that, when executed by the processor or processor core, cause the processor or processor core to bypass a first port stage in the instruction pipeline of the microprocessor to a second port stage by using at least one bypass of the one or more late bypasses.

19. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or processor core executing one or more threads, causes the at least one processor or processor core to perform a plurality of acts for implementing a microprocessor with a selective register file bypass network, the plurality of acts comprising:

removing late bypasses from a register file bypass network of a microprocessor design;

automatically adding one or more late bypasses, which are a smaller subset of the late bypasses removed, to the register file bypass network based at least in part upon analysis results of a plurality of instructions to be processed in an instruction pipeline of the microprocessor; and

generating an electronic design for at least the register file bypass network with the one or more late bypasses that are automatically added to the register file bypass network to reduce an area on silicon occupied by the electronic design or to improve performance of the microprocessor design.

20. The article of manufacture of claim 19, the plurality of acts further comprising:

sharing at least one bypass of the one or more late bypasses among a plurality of free-riders.

21. The article of manufacture of claim 19, the plurality of acts further comprising:

bypassing a first port stage in the instruction pipeline of the microprocessor to a second port stage by using at least one bypass of the one or more late bypasses.