Use of error correction pointers to handle errors in memory

• US 9,250,990 B2
• Filed: 09/24/2013
• Issued: 02/02/2016
• Est. Priority Date: 09/24/2013
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Motwani, Ravi H., Pangal, Kiran
• Primary Examiner(s): Kerveros, James C
• Application Number:
  US14/129,070
• Publication Number:
  US 20150089310A1
• Time in Patent Office: 861 Days
• Field of Search: 714/758, 714/764
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature

Abstract

Methods, apparatuses, and systems related to use of error correction pointers (ECPs) to handle hard errors in memory are described herein. In embodiments, a read module of a memory controller may read a codeword stored in a memory. The read module may determine a number of hard errors in the codeword. Responsive to a determination that the number of hard errors exceeds a threshold, the read module may store ECP information associated with the hard errors. The read module may include an error correction code (ECC) module to perform an ECC process on the codeword. The read module may use the ECP information to decode the codeword to recover the data responsive to a determination that the ECC process failed. Other embodiments may be described and claimed.

Claims

1. An apparatus for reading data from a memory, the apparatus comprising:

an error correction pointer (ECP) block to store a plurality of ECP pointers including ECP information associated with hard errors of one or more codewords associated with data stored in a memory; and

a memory controller including a read module coupled with the ECP block to read data stored in the memory, wherein to read data stored in the memory includes;

determine whether a number of hard errors in a codeword read from the memory exceeds a threshold; and

responsive to a determination that the number of hard errors in the codeword exceeds the threshold, update the ECP information associated with the hard errors of the codeword in one or more of the ECPs.

2. The apparatus of claim 1, wherein the read module includes an error correction code (ECC) module to perform an ECC process on the codeword, and wherein the read module is further to use the ECP information associated with hard errors of the codeword to decode the codeword responsive to a determination that the ECC process failed.

3. The apparatus of claim 2, wherein the threshold is less than a number of hard errors that are correctable by the ECC process.

4. The apparatus of claim 2, wherein the ECC process is a first ECC process, and wherein the ECC module is further to perform a second ECC process on the codeword using the ECP information.

5. The apparatus of claim 4, wherein the read module is configured to use a redundant array of independent silicon elements (RAISE) to decode the codeword if the second ECC process fails.

6. The apparatus of claim 1, wherein the threshold is a first threshold, and wherein the read module is to further:

determine that the number of hard errors in the codeword exceeds a second threshold that is higher than the first threshold; and

responsive to the determination that the number of hard errors exceeds the second threshold, retire memory cells of the memory associated with the codeword from further use.

7. The apparatus of claim 1, wherein the read module is to further determine that the memory has a bus failure based on ECP information associated with a plurality of codewords stored in the memory.

8. The apparatus of claim 1, wherein the memory is a phase change memory or a cross-point memory.

9. The apparatus of claim 1, wherein the ECP block is included in the memory controller.

10. The apparatus of claim 1, wherein the ECP information include an identifier of the codeword identifying where the codeword is stored in the memory, or indicating bits of the codeword that include hard errors and correct values of those bits, and wherein the ECPs is arranged in a binary tree in the ECP block.

11. A method for reading data from a memory comprising:

reading, by a read module of a memory controller apparatus, data from a codeword stored in a memory;

performing, by the read module, an error correction code (ECC) process on the codeword;

determining, by the read module, that the ECC process failed to successfully decode the codeword to recover the data;

responsive to the determination that the ECC process failed, reading, by the read module, error correction pointer (ECP) information associated with the codeword from one or more ECPs stored in an ECP block of the apparatus; and

decoding, by the read module, the codeword to recover the data based on the ECP information in the ECP stored in the ECP block.

12. The method of claim 11, further comprising:

determining, by the read module, a number of hard errors in the codeword;

determining, by the read module, that the number of hard errors in the codeword exceeds a threshold; and

responsive to the determination that the number of hard errors in the codeword exceeds the threshold, updating the ECP information associated with the codeword.

13. The method of claim 12, wherein the threshold is less than a number of hard errors that are correctable by the ECC process.

14. The method of claim 12, wherein the threshold is a first threshold, and wherein the method further comprises:

determining, by the read module, that the number of hard errors in the codeword exceeds a second threshold that is higher than the first threshold; and

retiring, by the read module, memory cells associated with the codeword from further use responsive to the determination that the number of hard errors exceeds the second threshold.

15. The method of claim 11, further comprising analyzing, by the read module, ECP information associated with a plurality of codewords of the memory to determine that the memory has a bus failure.

16. The method of claim 11, wherein the ECC process is a first ECC process, and wherein the method further comprises:

performing, by the read module, a second ECC process on the codeword based on the ECP information;

determining, by the read module, that the second ECC process failed; and

performing, by the read module, a redundant array of independent silicon elements (RAISE) to decode the codeword to recover the data responsive to the determination that the second ECC process failed.

17. A system for computing, the system comprising:

a memory to store a plurality of codewords including a first codeword;

an error correction pointer (ECP) block to store a plurality of ECP pointers including ECP information associated with hard errors of one or more codewords assocaited with data stored in the memory; and

a memory controller including a read module coupled to the memory and the ECP block to;

read the first codeword from the memory;

determine that the codeword was successfully decoded;

determine a number of hard errors in the first codeword responsive to the determination that the codeword was successfully decoded;

determine that the number of hard errors in the first codeword exceeds a threshold; and

responsive to the determination that the number of hard errors in the first codeword exceeds the threshold, store error correction pointer (ECP) information associated with hard errors of the first codeword in one or more of the ECPs stored in the ECP block.

18. The system of claim 17, wherein the read module includes an error correction code (ECC) module to perform an ECC process on the first codeword, and wherein the read module is further to use the ECP information to decode the first codeword responsive to a determination that the ECC process failed.

19. The system of claim 18, wherein the threshold is less than a number of hard errors that are correctable by the ECC process.

20. The system of claim 18, wherein the ECC process is a first ECC process, wherein the ECC module is further to perform a second ECC process on the codeword decoded using the ECP information, and wherein the read module is to further use a redundant array of independent silicon elements (RAISE) to decode the codeword responsive to a determination that the second ECC process failed.

21. The system of claim 17, wherein the threshold is a first threshold, and wherein the read module is to further:

determine that the number of hard errors in the first codeword exceeds a second threshold that is higher than the first threshold; and

responsive to the determination that the number of hard errors exceeds the second threshold, retire memory cells of the memory associated with the first codeword from further use.

22. The system of claim 17, wherein the read module is to further determine that the memory has a bus failure based on ECP information associated with the plurality of codewords of the memory.

23. The system of claim 17, wherein the memory is a phase change memory or a cross-point memory.

24. The system of claim 17, wherein the ECP information include an identifier of the codeword identifying where the codeword is stored in the memory, or indicating bits of the codeword that include hard errors and correct values of those bits, and wherein the ECPs is arranged in a binary tree in the ECP block.