Semiconductor memory device including non-volatile memory, cache memory, and computer system

• US 9,250,997 B2
• Filed: 03/08/2013
• Issued: 02/02/2016
• Est. Priority Date: 11/27/2012
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwon, Young-jun, Choi, Ki-young, Kim, Sun-gyeum, Kwon, Hyeok-man, Ahn, Jun-whan
• Primary Examiner(s): Rizk, Sam
• Application Number:
  US13/790,113
• Publication Number:
  US 20140149827A1
• Time in Patent Office: 1,061 Days
• Field of Search: 714/764, 711/103
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1677 Verifying circuits or methods
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In one embodiment, the memory device includes a data storage region and an error correction (ECC) region. The data storage region configured to store a first number of data blocks. The ECC region is configured to store a second number of ECC blocks. Each of the second number of ECC blocks is configured to store ECC information. The second number of the ECC blocks is associated with the first number of data blocks, and the second number is less than the first number.

Claims

1. A memory device, comprising:

a data storage region configured to store a first number of data blocks;

an error correction (ECC) region configured to store a second number of ECC blocks, each of the second number of ECC blocks configured to store ECC information, the second number of the ECC blocks being associated with the first number of data blocks, and the second number being less than the first number such that at least one of the data blocks does not have an ECC block associated therewith; and

an access circuit configured to,

receive a request to write received data to one of the first number of data blocks,

write the received data in the one of the first number of data blocks,

invalidate an ECC block associated with another data block to generate an invalidated ECC block,

write ECC data associated with the received data into the invalidated ECC block, and

validate the invalidated ECC block.

2. The memory device of claim 1, wherein the ECC region is configured to store validity information for each of the second number of ECC blocks, the validity information indicating whether a corresponding ECC block is valid.

3. The memory device of claim 2, wherein the ECC region is configured to store block identification information for each of the second number of ECC blocks, the block identification information indicating to which of the first number of data blocks an associated one of the second number of ECC blocks corresponds.

4. The memory device of claim 3, wherein the ECC region is configured to store timing information for each of the second number of ECC blocks, the timing information indicating an age of an associated one of the ECC blocks relative to others of the ECC blocks.

5. The memory device of claim 3, wherein

the ECC region includes a plurality of memory cell arrays, and the second number of ECC blocks, the validity information;

and

the block identification information are stored in different ones of the plurality of memory cell arrays.

6. The memory device of claim 5, wherein the second number of ECC blocks, the validity information and the block identification information are linked.

7. The memory device of claim 6, wherein the second number of ECC blocks, the validity information and the block identification information are linked based on how the second number of ECC blocks, the validity information and the block identification information are indexed in their respective memory cell arrays.

8. The memory device of claim 1, wherein the ECC region is configured to store block identification information for each of the second number of ECC blocks, the block identification information indicating to which of the first number of data blocks an associated one of the second number of ECC blocks corresponds.

9. The memory device of claim 8, wherein the access circuit is further configured to,

write to and read from the data storage region and the ECC region;

receive a request to read one of the first number of data blocks;

read the requested data block;

determine from the block identification information if one of the second number of ECC blocks is associated with the requested data block; and

if one of the second number of ECC blocks is associated with the requested data block,

read the associated ECC block; and

perform error correction on the read data block using the read ECC block.

10. The memory device of claim 1, wherein the second number is one.

11. The memory device of claim 1, wherein the first number of data blocks and the second number of ECC blocks form a page.

12. The memory device of claim 11, wherein the second number is one.

13. The memory device of claim 1, wherein the data storage region and the ECC region include a plurality of memory cells, and the plurality of memory cells include MRAM memory cells.

14. The memory device of claim 13, wherein the memory device is a cache.

15. The memory device of claim 1, wherein the memory device is a cache.

16. The memory device of claim 15, wherein the data storage region is n-way set associative, where n is the first number.

17. The memory device of claim 1, wherein the access circuit configured to,

receive the request to write the received data to the one of the first number of data blocks;

determine if the written data includes errors that are not correctable by the ECC data; and

correct at least one of the errors in the written data by rewriting the received data if the errors are determined not to be correctable.

18. The memory device of claim 17, wherein the data storage region and the ECC region include a plurality of memory cells, and the plurality of memory cells include MRAM memory cells.

19. The memory device of claim 18, wherein the memory device is a cache.

20. A memory device, comprising:

a data storage region configured to store a first number of data blocks;

an error correction (ECC) region configured to store a second number of ECC blocks, each of the second number of ECC blocks configured to store ECC information, the second number of the ECC blocks being associated with the first number of data blocks, and the second number being less than the first number; and

an access circuit configured to write to and read from the data storage region and the ECC region, the access circuit configured to,

receive a request to write received data to a selected one of the first number of data blocks;

determine if an invalid error correction (ECC) block in the second number of ECC blocks exists in response to the request; and

if an invalid ECC block does not exist,

remove errors from data in another of the first data blocks such that no errors in reading the another data block exist;

invalidate the ECC block associated with the another data block;

write the received data in the selected data block;

write ECC data associated with the received data into the invalidated ECC block; and

change a state of the invalidated ECC block to valid.

21. The memory device of claim 20, wherein in changing the state of the invalidated ECC block, the access circuit is configured to store validity information in association with the invalidated ECC block.

22. The memory device of claim 20, wherein if an invalid ECC block does not exist, the access circuit is configured to store block identification information in association with the valid ECC block, the block identification information indicating to which of the first number of data blocks the valid ECC block corresponds.

23. The memory device of claim 22, wherein if an invalid ECC block does not exist, the access circuit is configured to store timing information in association with the valid ECC block, the timing information indicating an age of an associated one of the second number of ECC blocks relative to others of the second number of ECC blocks.

24. The memory device of claim 23, wherein the timing information is a count value, and the storing timing information includes changing the count value associated with other valid ECC blocks.

25. The memory device of claim 24, wherein in the removing errors, the access circuit is configured to remove errors from one of the first number of data blocks associated with one of the second number of ECC blocks having a highest count value.

26. The memory device of claim 23, wherein in the removing errors, the access circuit is configured to remove errors from a one of the first number of data blocks corresponding to an oldest ECC block as indicated by the timing information.

27. The memory device of claim 20, wherein in the removing errors, the access circuit is configured to randomly select the another data block.

28. The memory device of claim 20, wherein if an invalid ECC block does exist, the access circuit is configured to,

write the received data to the selected data block;

write ECC data associated with the received data to an invalid one of the second number of ECC blocks;

determine if the written data includes errors; and

invalidate the ECC block in which the ECC data was written if the determining determines that the written data does not include errors.

29. The memory device of claim 28, wherein if the access circuit determines the written data does include errors, the access circuit is configured to,

determine if the errors are not correctable by the ECC data;

and

correct at least one of the errors in the written data by rewriting the received data if the errors are determined not to be correctable.

30. The memory device of claim 29, wherein the access circuit is configured to validate the ECC block if the errors are determined to be correctable.