Apparatus, system and method for autonomous recovery from failures during system characterization on an environment with restricted resources

• US 9,251,006 B2
• Filed: 12/23/2013
• Issued: 02/02/2016
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Packer Ali, Dhamim, Wang, Tom C., Liu, Sha, Chalamcharla, Sreenivasulu Reddy
• Primary Examiner(s): Ehne, Charles
• Application Number:
  US14/139,704
• Publication Number:
  US 20150149810A1
• Time in Patent Office: 771 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1492 by run-time replication performed by the application software
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

Claims

1. A computing device, comprising:

a primary boot loader responsive to at least two separate start conditions;

a processor, coupled to and responsive to the primary boot loader;

a set of storage devices coupled to the processor, a first member of the set of storage devices exhibited in a cache, and a second member of the set of storage devices exhibited in integrated circuits that share a circuit substrate with the processor; and

an integrated power management module that selectively responds to a computing device condition defining a system fault, wherein the integrated power management module maintains power rails that supply at least the processor and the second member of the set of storage devices when a watchdog reset signal is detected.

2. The computing device of claim 1, wherein the primary boot loader initializes the computing device by defining the first member of the set of storage devices as a dedicated memory for static data.

3. The computing device of claim 1, wherein the primary boot loader initializes the computing device in a download mode in response to an error loading an image from a flash-based storage media.

4. The computing device of claim 1, wherein the primary boot loader is responsive to an input that defines a download mode.

5. The computing device of claim 4, wherein the input that defines the download mode is communicated via an eFuse element or a general-purpose input output bus.

6. The computing device of claim 4, wherein when the download mode is enabled and in response to a separate signal, the primary boot loader authenticates processor executable logic.

7. The computing device of claim 4, wherein when the input that defines the download mode is present, the primary boot loader loads processor executable logic into the first member of the set of storage devices and directs the processor to process the processor executable logic.

8. The computing device of claim 7, wherein the processor executable logic directs the processor to store the processor executable logic and a present device status to a first defined location in the second member of the set of storage devices, the processor executable logic further directing the processor to insert logic at a second defined location in the second member of the set of storage devices that can be accessed in response to a device reset.

9. The computing device of claim 8, wherein the second defined location includes an address of the copy of the processor executable logic and the copy of the present device status.

10. A method for autonomous recovery from system failures in a computing device with restricted capacity data storage resources, the method comprising:

arranging an integrated circuit with a selective power management module;

providing integrated read-only logic arranged to initialize the computing device, the integrated read-only logic defining a cache storage element to function as an integrated memory element to store static information including executable logic received from an external source and a present device status;

using the cache storage element to relocate a copy of the executable logic and the present device status to a first location in an internal memory element;

using the cache storage element to insert information in a second location in the internal memory element, the information including the first location in the internal memory element; and

using the integrated read-only logic to detect a condition indicative of a failure and direct a processor to use the information in the second location in the internal memory element to jump to the first location in the internal memory element upon recovery from the failure.

11. The method of claim 10, wherein arranging the integrated circuit with the selective power management module includes maintaining supply power to at least one core of the processor and the internal memory element.

12. The method of claim 10, wherein the integrated read-only logic responds in a first way to a first condition and in a second way to a reset condition.

13. The method of claim 10, wherein the integrated read-only logic authenticates a source of the executable logic.

14. The method of claim 10, wherein the executable logic is arranged to characterize the computing device and store results in the second location in the internal memory element.

15. The method of claim 14, wherein the executable logic records results for varying supply voltage and environmental conditions independent of an external computing system.

16. A non-transitory processor-readable medium having stored thereon processor instructions that when executed direct the processor to perform functions, comprising:

configuring a computing device responsive to one of a download mode of operation that receives processor executable logic from a source other than the computing device or an attempt to record parameters responsive to at least one variable test condition that resulted in an indication of a failure recorded on the computing device;

executing the processor executable logic from the source other than the computing device;

identifying a failure condition;

upon recovering from the failure condition, restoring the processor executable logic and a state of the computing device when the failure condition is indicated; and

executing the next instruction from the processor executable logic.

17. The non-transitory processor-readable medium of claim 16, wherein configuring the computing device includes dedicating a portion of a cache for storage of static data.

18. The non-transitory processor-readable medium of claim 16, wherein configuring the computing device is responsive to an input received via a general-purpose input output bus or an eFuse.

19. The non-transitory processor-readable medium of claim 16, wherein configuring the computing device includes enabling a download mode in response to an error loading an image from a flash-based storage media.