Memory system providing wear-leveling by allocating memory blocks among groups
First Claim
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1. A flash memory system comprising:
- a memory controller configured to selectively allocate a plurality of memory blocks of a flash memory device among a plurality of groups of memory blocks such that,from among the plurality of memory blocks, memory blocks having an erase count less than a threshold erase count are allocated to a first of the plurality of groups of memory blocks,from among the plurality of memory blocks, memory blocks having an erase count greater than the threshold erase count are allocated to a second of the plurality of groups of memory blocks, andfrom among the plurality of memory blocks, memory blocks having a number of errors in data greater than a threshold number of errors in data are allocated to a third of the plurality of groups of memory blocks;
wherein the first of the plurality of groups of memory blocks has a higher priority than the second and third of the plurality of groups of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the first of the plurality of groups of memory blocks are utilized prior to memory blocks allocated to the second and third of the plurality of groups of memory blocks.
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Abstract
Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.
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Citations
18 Claims
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1. A flash memory system comprising:
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a memory controller configured to selectively allocate a plurality of memory blocks of a flash memory device among a plurality of groups of memory blocks such that, from among the plurality of memory blocks, memory blocks having an erase count less than a threshold erase count are allocated to a first of the plurality of groups of memory blocks, from among the plurality of memory blocks, memory blocks having an erase count greater than the threshold erase count are allocated to a second of the plurality of groups of memory blocks, and from among the plurality of memory blocks, memory blocks having a number of errors in data greater than a threshold number of errors in data are allocated to a third of the plurality of groups of memory blocks; wherein the first of the plurality of groups of memory blocks has a higher priority than the second and third of the plurality of groups of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the first of the plurality of groups of memory blocks are utilized prior to memory blocks allocated to the second and third of the plurality of groups of memory blocks. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory system comprising:
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a memory controller configured to, allocate at least a first of a plurality of memory blocks of a flash memory device from a first group of memory blocks to a second group of memory blocks based on a number of erasures of the first of the plurality of memory blocks, allocate at least a second of the plurality of memory blocks from the first group of memory blocks to a third group of memory blocks based on a number of errors in data associated with the second of the plurality of memory blocks, and allocate at least a third of the plurality of memory blocks from the second group of memory blocks to the third group of memory blocks based on a number of errors in data associated with the third of the plurality of memory blocks; wherein the first group of memory blocks has a higher priority than the second and third groups of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the first group of memory blocks are utilized prior to memory blocks allocated to the second and third groups of memory blocks. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification