Memory system providing wear-leveling by allocating memory blocks among groups

• US 9,251,015 B2
• Filed: 05/09/2014
• Issued: 02/02/2016
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yim, Yong-Tae, Jo, Sung-Kue
• Primary Examiner(s): SCHELL, JOSEPH O
• Application Number:
  US14/273,901
• Publication Number:
  US 20140245109A1
• Time in Patent Office: 634 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

Provided is a memory system and wear-leveling method. A memory system includes a flash memory device and a memory controller. The flash memory device includes a plurality of memory blocks, each including a plurality of memory cells. The memory controller is configured to control the flash memory device based on erase event information and error checking and correction (ECC) event information of each of the memory blocks such that use of the memory blocks is distributed more uniformly.

Claims

1. A flash memory system comprising:

a memory controller configured to selectively allocate a plurality of memory blocks of a flash memory device among a plurality of groups of memory blocks such that,

from among the plurality of memory blocks, memory blocks having an erase count less than a threshold erase count are allocated to a first of the plurality of groups of memory blocks,

from among the plurality of memory blocks, memory blocks having an erase count greater than the threshold erase count are allocated to a second of the plurality of groups of memory blocks, and

from among the plurality of memory blocks, memory blocks having a number of errors in data greater than a threshold number of errors in data are allocated to a third of the plurality of groups of memory blocks;

wherein the first of the plurality of groups of memory blocks has a higher priority than the second and third of the plurality of groups of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the first of the plurality of groups of memory blocks are utilized prior to memory blocks allocated to the second and third of the plurality of groups of memory blocks.

2. The memory system of claim 1, wherein the memory controller is configured to allocate at least a first of the plurality of memory blocks from the first of the plurality of groups of memory blocks to the second of the plurality of groups when the erase count for the first of the plurality of memory blocks exceeds the threshold erase count.

3. The memory system of claim 2, wherein the memory controller is further configured to allocate at least the first of the plurality of memory blocks from the second of the plurality of groups of memory blocks to the third of the plurality of groups of memory blocks when a number of errors in data associated with the first of the plurality of memory blocks exceeds the threshold number of errors in data.

4. The memory system of claim 1, wherein the memory controller is configured to allocate at least a first of the plurality of memory blocks from the first of the plurality of groups of memory blocks to the third of the plurality of groups of memory blocks when a number of errors in data associated with the first of the plurality of memory blocks exceeds the threshold number of errors in data.

5. The memory system of claim 1, wherein the memory controller is configured to allocate at least a first of the plurality of memory blocks from the second of the plurality of groups of memory blocks to the third of the plurality of groups of memory blocks when a number of errors in data associated with the first of the plurality of memory blocks exceeds the threshold number of errors in data.

6. The memory system of claim 1, wherein the second of the plurality of groups of memory blocks has a higher priority than the third of the plurality of groups of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the second of the plurality of groups of memory blocks are utilized prior to memory blocks allocated to the third of the plurality of groups of memory blocks.

7. The memory system of claim 1, further comprising:

the flash memory device including the plurality of memory blocks, each of the plurality of memory blocks including at least one memory cell.

8. The memory system of claim 7, wherein the flash memory device and the memory controller constitute a solid state drive (SSD).

9. A computing system comprising:

the memory system of claim 1; and

a microprocessor configured to interact with the memory controller to store data in the flash memory device.

10. A memory system comprising:

a memory controller configured to,

allocate at least a first of a plurality of memory blocks of a flash memory device from a first group of memory blocks to a second group of memory blocks based on a number of erasures of the first of the plurality of memory blocks,

allocate at least a second of the plurality of memory blocks from the first group of memory blocks to a third group of memory blocks based on a number of errors in data associated with the second of the plurality of memory blocks, and

allocate at least a third of the plurality of memory blocks from the second group of memory blocks to the third group of memory blocks based on a number of errors in data associated with the third of the plurality of memory blocks;

wherein the first group of memory blocks has a higher priority than the second and third groups of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the first group of memory blocks are utilized prior to memory blocks allocated to the second and third groups of memory blocks.

11. The memory system of claim 10, wherein the second group of memory blocks has a higher priority than the third group of memory blocks, such that, in response to an external command from a host, memory blocks allocated to the second group of memory blocks are utilized prior to memory blocks allocated to the third group of memory blocks.

12. The memory system of claim 10, wherein the memory controller is further configured to allocate at least the first of the plurality of memory blocks from the first group of memory blocks to the second group of memory blocks when the number of erasures of the first of the plurality of memory blocks exceeds a threshold number of erasures.

13. The memory system of claim 10, wherein the memory controller is further configured to allocate at least the second of the plurality of memory blocks from the first group of memory blocks to the third group of memory blocks when the number of errors in data associated with the second of the plurality of memory blocks exceeds a threshold number of errors in data.

14. The memory system of claim 13, wherein the memory controller is further configured to allocate the third of the plurality of memory blocks from the second group of memory blocks to the third group of memory blocks when the number of errors in data associated with the third of the plurality of memory blocks exceeds the threshold number of errors in data.

15. The memory system of claim 10, wherein the memory controller is further configured to allocate the third of the plurality of memory blocks from the second group of memory blocks to the third group of memory blocks when the number of errors in data associated with the third of the plurality of memory blocks exceeds a threshold number of errors in data.

16. The memory system of claim 10, further comprising:

the flash memory device including the plurality of memory blocks, each of the plurality of memory blocks including at least one memory cell.

17. The memory system of claim 16, wherein the flash memory device and the memory controller constitute a solid-state drive (SSD).

18. A computing system comprising:

the memory system of claim 10; and

a microprocessor configured to interact with the memory controller to store data in the flash memory device.