Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs

• US 9,251,299 B1
• Filed: 06/28/2013
• Issued: 02/02/2016
• Est. Priority Date: 06/28/2013
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Salowe, Jeffrey S.
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US13/931,689
• Time in Patent Office: 949 Days
• Field of Search: 716/55
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

One aspect creates or identifies a rule, identifies or creates track pattern(s), and associate the rule with the track pattern(s). The rule is used to guide physical implementation tools to implement electronic designs which not only satisfy the constraints of the rule but also the constraints of the track pattern(s). Some other aspects are directed at interpretation or automatic association or assignment of a layer constraint by determining whether a track pattern on a layer with a first rule matches a second rule, and adding the track pattern to the layer constraint for the second rule on the layer. Another aspect is directed at automatic creation of a rule by creating a new rule, examining each track pattern associated with a first rule, determining whether the new rule matches the first rule, and adding the track pattern to a layer constraint for the new rule.

Claims

1. A computer implemented method for implementing an electronic design with track patterns, comprising:

identifying or creating, with a design rule module that is at least partially stored in memory and includes or is coupled with at least one processor or at least one processor core of a computing system, a rule that includes a first requirement for implementation of an electronic design;

identifying or creating a track pattern, wherein

the track pattern comprises a plurality of tracks and a specification of one or more permissible interconnect width values for the plurality of tracks that are used to aid the implementation of the electronic design, and

at least one of the plurality of tracks includes a zero-width line segment on which a centerline of an interconnect lies; and

associating the rule with the track pattern.

2. The computer implemented method of claim 1, the process further comprising:

identifying or creating an identifier for the track pattern; and

creating or updating a constraint by using at least the identifier of the track pattern.

3. The computer implemented method of claim 1, wherein the rule is used to guide one or more physical implementation tools that implement the electronic design, and the physical implementation tools include a floorplanner, a placement tool, a routing tool, a post-route optimization tool, and an engineering change order tool.

4. The computer implemented method of claim 1, the process further comprising:

creating a non-uniform track pattern by aggregating multiple track patterns, wherein the non-uniform track pattern comprises tracks associated with different geometric attributes or different constraints.

5. The computer implemented method of claim 4, the process further comprising:

identifying or creating an identifier for the non-uniform track pattern; and

updating each declaration of the multiple track patterns with the identifier of the non-uniform track pattern.

6. The computer implemented method of claim 1, the act of associating the rule with the track pattern comprising:

creating a constraint that is used to guide physical implementation of the electronic design and includes an identifier of the track pattern and a requirement of the rule, wherein

the requirement of the rule is used to determine whether the rule is to be associated with the track pattern.

7. A system for implementing an electronic design with track patterns, comprising:

a computing system having at least one processor or at least one processor core;

a memory storing thereupon a sequence of instructions which, when executed by the at least one processor or the at least one processor core, cause the at least one processor or the at least one processor core at least to;

identify or create a rule that includes a first requirement for implementation of an electronic design;

identify or create a track pattern, wherein

the track pattern comprises a plurality of tracks and a specification of one or more permissible interconnect width values for the plurality of tracks that are used to aid the implementation of the electronic design, and

at least one of the plurality of tracks includes a zero-width line segment on which a centerline of an interconnect lies; and

associate the rule with the track pattern.

8. The system of claim 7, wherein the at least one processor or at least one processor core is further to:

identify or create an identifier for the track pattern; and

create or update a constraint by using at least the identifier of the track pattern.

9. The system of claim 7, wherein the at least one processor or at least one processor core is further to:

create a non-uniform track pattern by aggregating multiple track patterns, wherein the non-uniform track pattern comprises tracks associated with different geometric attributes or different constraints;

identify or create a identifier for the non-uniform track pattern; and

update each declaration of the multiple track patterns with the identifier of the non-uniform track pattern.

10. The system of claim 7, wherein the at least one processor or the at least one processor core that is to associate the rule with the track pattern is further to:

create a constraint that is used to guide physical implementation of the electronic design and includes an identifier of the track pattern and a requirement of the rule.

11. An article of manufacture comprising a non-transitory computer accessible storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor or at least one processor core executing one or more threads, causes the at least one processor or the at least one processor core to perform a method for implementing an electronic design with track patterns, the method comprising:

identifying or creating, with a design rule module that is at least partially stored in memory and includes or is coupled with at least one processor or at least one processor core of a computing system, a rule that includes a first requirement for implementation of an electronic design;

identifying or creating a track pattern, wherein

the track pattern comprises a plurality of tracks and a specification of one or more permissible interconnect width values for the plurality of tracks that are used to aid the implementation of the electronic design, and

at least one of the plurality of tracks includes a zero-width line segment on which a centerline of an interconnect lies; and

associating the rule with the track pattern.

12. The article of manufacture of claim 11, the process further comprising:

identifying or creating an identifier for the track pattern; and

creating or updating a constraint by using at least the identifier of the track pattern.

13. The article of manufacture of claim 11, the process further comprising:

creating a non-uniform track pattern by aggregating multiple track patterns, wherein the non-uniform track pattern comprises tracks associated with different geometric attributes or different constraints;

identifying or creating a identifier for the non-uniform track pattern; and

updating each declaration of the multiple track patterns with the identifier of the non-uniform track pattern.

14. The article of manufacture of claim 11, the act of associating the rule with the track pattern comprising:

creating a constraint that is used to guide physical implementation of the electronic design and includes an identifier of the track pattern and a requirement of the rule.

15. A computer implemented method for implementing an electronic design with track patterns, comprising:

identifying or creating, with a design rule module that is at least partially stored in memory and includes or is coupled with at least one processor or at least one processor core of a computing system, a track pattern, wherein

the track pattern comprises a plurality of tracks and a specification of one or more permissible interconnect width values for the plurality of tracks that are used to aid implementation of the electronic design, and

at least one of the plurality of tracks includes a zero-width line segment on which a centerline of an interconnect lies;

identifying or creating a rule that is used to guide the implementation of the electronic design;

determining whether the track pattern matches the rule; and

associating the track pattern with the rule.

16. The computer implemented method of claim 15, the act of determining whether the track pattern matches the rule comprising:

identifying a first constraint that is associated with the track pattern;

identifying a relevant part of the first constraint associated with the track pattern;

identifying a corresponding part, which corresponds to the relevant part of the first constraint, of the rule; and

determining whether the relevant part of the first constraint matches the corresponding part of the rule.

17. The computer implemented method of claim 15, the process further comprising:

identifying or creating an identifier of the track pattern; and

creating or updating declaration of the track pattern by adding the identifier to the declaration of the track pattern.

18. The computer implemented method of claim 15, the process further comprising:

determining whether there is an addition rule to be processed;

identifying the additional rule;

determining whether the track pattern matches the addition rule; and

associating the track pattern with the additional rule.

19. The computer implemented method of claim 15, the process further comprising:

determining whether there is an addition track pattern to be processed;

identifying the addition track pattern;

determining whether the additional track pattern matches the rule; and

associating the additional track pattern with the rule.

20. The computer implemented method of claim 15, the process further comprising:

aggregating multiple track patterns to create an aggregated track pattern;

identifying or creating an identifier for the aggregated track pattern; and

updating each declaration of the multiple track patterns with the identifier of the aggregated track pattern.