Block-based signal processing

• US 9,251,554 B2
• Filed: 12/26/2012
• Issued: 02/02/2016
• Est. Priority Date: 12/26/2012
• Status: Active Grant

• Current Assignee: Analog Devices, Inc.
• Original Assignee: Analog Devices, Inc.
• Inventors: Singh, Raka
• Primary Examiner(s): AMINI, JAVID A
• Application Number:
  US13/727,208
• Publication Number:
  US 20140176571A1
• Time in Patent Office: 1,133 Days
• Field of Search: 345/501
• US Class Current: 1/1
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Signal flows for data-processing applications may be implemented so as to enable each processing node in the flow when it contains a sufficient amount of input data at its input buffer. In various embodiments, such signal flows can be graphically defined in a GUI tool which, thereafter, auto-generates suitable code for implementing the signal flow.

Claims

1. A storage-efficient method for processing frame data, comprising:

receiving, from a first processing node in a series of processing nodes implemented by one or more computing devices, data at an input buffer associated with a second processing node in the series, wherein the second processing node in the series is to perform an operation that requires an input that is a block of frame data of a first predetermined size to generate a block of frame data of a second predetermined size, and the first and second predetermined sizes each comprise a plurality of frame data samples;

determining, by the one or more computing devices, that a size of the data in the input buffer is equal to the first predetermined size; and

in response to determining that the size of the data in the input buffer is equal to the first predetermined size, causing, by the one or more computing devices, the second processing node to operate on the frame data in the input buffer to generate a block of frame data of the second predetermined size.

2. The method of claim 1, wherein the frame data is image frame data.

3. The method of claim 2, wherein the second predetermined size is one row of an image frame.

4. The method of claim 3, wherein the first predetermined size is multiple rows of an image frame.

5. The method of claim 1, wherein the first processing node is a direct memory access (DMA) source node.

6. The method of claim 1, further comprising re-using memory allocated to the input buffer for another buffer associated with another processing node in the series, wherein the another node is different from the first processing node and the second processing node.

7. The method of claim 1, further comprising causing operation of multiple processing nodes in the series in parallel.

8. The method of claim 1, further comprising causing operation of the processing nodes in the series sequentially.

9. The method of claim 1, wherein determining that a size of the data in the input buffer is equal to the first predetermined size comprises:

maintaining a counter for the input buffer; and

incrementing the counter in response to receipt of units of data from the first processing node.

20. The method of claim 1, wherein the second processing node is to provide the generated block of frame data of the second predetermined size to a direct memory access (DMA) sink node.

21. The method of claim 1, wherein the first processing node is to generate the block of frame data of the second predetermined size by performance of a filtering operation on the block of frame data of the first predetermined size.

22. The method of claim 1, wherein receiving, from the first processing node in the series of processing nodes, data at an input buffer associated with the second processing node in the series, comprises receiving a block of frame data having a size that is smaller than the first predetermined size.

10. A storage-efficient system for processing frame data, comprising:

at least one computing device to provide first and second processing nodes, wherein the second processing node is to perform an operation that requires an input that is a block of frame data of a first predetermined size to generate a block of frame data of a second predetermined size, and the first and second predetermined sizes each comprise a plurality of frame data samples;

an input buffer associated with the second processing node, wherein the input buffer is sized to store an amount of frame data that is greater than or equal to the first predetermined size; and

a logic switching mechanism to cause execution of the second processing node, by the at least one computing device, to operate on the frame data in the input buffer when the input buffer stores an amount of data equal to the first predetermined size.

11. The system of claim 10, wherein the logic switching mechanism comprises a register to store, for the second processing node, a representation of the first predetermined size and a counter for a number of blocks of the first predetermined size presently stored in the input buffer.

12. The system of claim 11, wherein the register is a hardware register.

13. The system of claim 11, wherein the register is stored in local memory associated with the at least one processing device.

14. The system of claim 10, wherein the at least one computing device includes a digital signal processor.

23. The system of claim 10, wherein the second predetermined size is smaller than the first predetermined size.

24. The system of claim 10, wherein the first processing node is a direct memory access (DMA) source node.

25. The system of claim 10, wherein the first predetermined size and the second predetermined size are different sizes.

26. The system of claim 10, wherein the first predetermined size is a first number of rows and the second predetermined size is a second number of rows.

15. One or more non-transitory computer readable media for generating program code for block-based processing of frame data from a graphical representation of a signal flow defined in a graphical user interface, wherein the one or more non-transitory computer readable media has stored thereon instructions that, in response to execution by one or more computing devices of a system, cause the system to:

provide a library of functions to implement signal-processing nodes, wherein a first function of the library of functions is to require an input that is a block of frame data of a first predetermined size to generate a block of frame data of a second predetermined size, wherein the first and second predetermined sizes each includes a plurality of frame data samples;

provide an editor to enable a user to graphically define a signal flow comprising a plurality of nodes and connections therebetween, and to associate with each of the nodes one of the functions from the library; and

provide a compiler to generate program code from the graphically defined signal flow and the associated functions, wherein a node in the graphically defined signal flow is associated with the first function, the program code is to cause, upon execution, operation of the node to generate a block of frame data of the second predetermined size in response to a determination that a size of data stored in an input buffer associated with the node is equal to the first predetermined size.

16. The one or more non-transitory computer readable media of claim 15, wherein the editor is to enable the user to graphically define direct memory access (DMA) of the signal flow.

17. The one or more non-transitory computer readable media of claim 16, wherein the editor is to enable the user to define at least one of a DMA source, a DMA sink, or a DMA scheduling path.

18. The one or more non-transitory computer readable media of claim 16, wherein the compiler is to generate program code implementing the graphically defined DMA.

19. The one or more non-transitory computer readable media of claim 15, wherein the instructions are further to cause the system to provide the graphical user interface to a display device for display.

27. One or more non-transitory computer readable media having instructions thereon that, in response to execution by one or more processing devices of a computing system, cause the computing system to:

provide a first processing node; and

provide a second processing node, wherein the second processing node is to receive, from the first processing node, data at an input buffer associated with the second processing node, wherein the second processing node in the series is to perform an operation that requires an input that is a block of frame data of a first predetermined size to generate a block of frame data of a second predetermined size, and wherein the first and second predetermined sizes each comprise a plurality of frame data samples;

determine that a size of the data in the input buffer is equal to the first predetermined size; and

in response to a determination that the size of the data in the input buffer is equal to the first predetermined size, cause the second processing node to operate on the frame data in the input buffer to generate a block of frame data of the second predetermined size.

28. The one or more non-transitory computer readable media of claim 27, wherein the second predetermined size is an integer number of rows of an image frame.

29. The one or more non-transitory computer readable media of claim 27, wherein the first processing node is a direct memory access (DMA) source node.