Methods for promoting semiconductor manufacturing yield and classifying defects during fabricating a semiconductor device, and computer readable mediums encoded with a computer program implementing the same

• US 9,251,581 B1
• Filed: 03/28/2011
• Issued: 02/02/2016
• Est. Priority Date: 09/14/2010
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: Hermes Microvision, Inc. (ASML Holding NV)
• Inventors: Fang, Wei, Peng, Futang, Zhang, Zhao-Li, Chen, Shih-Tsung, Fu, Yu-Tsorng
• Primary Examiner(s): CHANG, JON CARLTON
• Application Number:
  US13/073,405
• Time in Patent Office: 1,772 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/001 using an image reference approach
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

A method for promoting semiconductor manufacturing yield comprising the following steps and a computer readable medium encoded with a computer program implementing the method is provided. First, a processed layer is inspected to generate an inspected image with defects thereon. Next, the inspected image is aligned to an original design layout information of the processed layer. In addition, the defects are classified according to geometric features of the original design layout information of the processed layer and at least previous one layer and/or at least next one layer.

Claims

1. A method for promoting semiconductor manufacturing yield of a multilayered device, comprising steps of:

inspecting a processed layer of the multilayered device to identify defects such that an inspected image with the defects thereon is generated;

aligning the inspected image to an original design layout information of the processed layer to determine the locations of the defects in the processed layer; and

classifying the defects on the inspected image according to the locations of the defects, patterned geometric features of the original design layout information of the processed layer and patterned geometric features of at least one previous layer and/or at least one next layer of the multilayered device.

2. The method as claimed in claim 1, further comprising defining at least one hotspot of the original design layout information according to at least one of the defects being classified as a defect of interest.

3. The method as claimed in claim 1, wherein the at least one previous layer, the processed layer, and the at least one next layer are formed on a semiconductor substrate sequentially.

4. The method as claimed in claim 1, wherein each of the at least one previous layer, the processed layer, and the at least one next layer is a metal layer, a semiconductor layer, a dielectric layer, or a photo resist layer.

5. A method for classifying defects during fabricating a semiconductor device, comprising steps of:

providing an inspected image with defects thereon, wherein the inspected image is generated from inspecting a processed layer of a semiconductor wafer inspected by a scanning electron microscope to identify the defects;

aligning the inspected image to an original design layout information of the processed layer to determine the locations of the defects in the processed layer; and

classifying the defects on the inspected image according to the locations of the defects, patterned geometric features of the original design layout information of the processed layer and patterned geometric features of at least one previous layer and/or at least one next layer of the semiconductor device.

6. The method as claimed in claim 5, further comprising defining at least one hotspot of the original design layout information according to at least one of the defects being classified as a defect of interest.

7. The method as claimed in claim 5, wherein the processed layer is a metal layer, a semiconductor layer, a dielectric layer or a photo resist layer.

8. A non-transitory computer readable medium encoded with a computer program implementing a method for promoting semiconductor manufacturing yield of a multilayered device and the method comprises steps of:

inspecting a processed layer of the multilayered device to identify defects such that an inspected image with the defects thereon is generated;

aligning the inspected image to an original design layout information of the processed layer to determine the locations of the defects in the processed layer; and

classifying the defects on the inspected image according to the locations of the defects, patterned geometric features of the original design layout information of the processed layer and patterned geometric features of at least one previous layer and/or at least one next layer of the multilayered device respectively.

9. The non-transitory computer readable medium as claimed in claim 8, wherein the method further comprises defining at least one hotspot of the original design layout information according to at least one of the defects being classified as a defect of interest.

10. The non-transitory computer readable medium as claimed in claim 8, wherein the at least one previous layer, the processed layer, and the at least one next layer are formed on a semiconductor substrate sequentially.

11. The non-transitory computer readable medium as claimed in claim 8, wherein each of the at least one previous layer, the processed layer, and the at least one next layer is a metal layer, a semiconductor layer, a dielectric layer, or a photo resist layer.

12. A non-transitory computer readable medium encoded with a computer program implementing a method for classifying defects during fabricating a semiconductor device and the method comprises steps of:

providing an inspected image with defects thereon, wherein the inspected image is generated from inspecting a processed layer of a semiconductor wafer inspected by a scanning electron microscope to identify the defects;

aligning the inspected image to an original design layout information of the processed layer to determine the locations of the defects in the processed layer; and

classifying the defects on the inspected image according to the locations of the defects, patterned geometric features of the original design layout information of the processed layer and patterned geometric features of at least one previous layer and/or at least one next layer of the semiconductor device.

13. The non-transitory computer readable medium as claimed in claim 12, wherein the method further comprises defining at least one hotspot of the original design layout information according to at least one of the defects being classified as a defect of interest.

14. The non-transitory computer readable medium as claimed in claim 12, wherein the processed layer is a metal layer, a semiconductor layer, a dielectric layer or a photo resist layer.