Methods and systems for pin-efficient memory controller interface using vector signaling codes for chip-to-chip communications

• US 9,251,873 B1
• Filed: 12/16/2013
• Issued: 02/02/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Holden, Brian, Shokrollahi, Amin, Singh, Anant, Fox, John, Surace, Giuseppe
• Primary Examiner(s): ABAD, FARLEY J
• Application Number:
  US14/108,316
• Time in Patent Office: 778 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are described for transmitting data over physical channels to provide a high speed, low latency interface such as between a memory controller and memory devices. Controller-side and memory-side embodiments of such channel interfaces are disclosed which require a low pin count and have low power utilization. In some embodiments of the invention, different voltage, current, etc. levels are used for signaling and more than two levels may be used, such as a vector signaling code wherein each wire signal may take on one of four signal values.

Claims

1. A device comprising:

a link layer signaling protocol control circuit configured to receive a plurality of memory transaction signals from a bus controller and responsively generate link layer bits, at a link layer interface, representing the memory transaction signals as a message packet, wherein the message packet is selected from the group consisting of a memory write packet, a memo read packet and a status interrogation command packet; and

,

a physical layer signaling protocol control circuit connected to the link layer interface and configured to receive the link layer bits, select a set of data bits from the link layer bits, form a code word of a vector signaling code based on the selected set of data bits, the code word comprising a first set of symbols, map the first set of symbols of the code word to a collection of interconnection signal lines and synchronize symbol communication via symbol clock lines.

2. The device of claim 1, wherein the collection of interconnection signal lines comprises four bidirectional data lines and two symbol clock lines.

3. The device of claim 2, wherein the physical layer signaling protocol control circuit communicates three data bits over the four data lines using a balanced code of symbols having four distinct signal levels.

4. The device of claim 3, wherein the collection of interconnection signal lines additionally comprises two clock lines carrying a return clock signal to the physical layer signaling protocol control circuit.

5. The device of claim 1, wherein the collection of interconnection lines comprises five bidirectional data lines and two symbol clock lines.

6. The device of claim 5, wherein the physical layer signaling protocol control circuit communicates three data bits over five lines, and the link layer protocol circuit is self-clocking in a memory-to-controller direction.

7. The device of claim 1, wherein the vector signaling code is an H4 signaling code.

8. The device of claim 1, wherein the physical layer signaling protocol control circuit is further configured to receive consecutive sets of symbols representing a second message packet via the connection of interconnection signal lines, the second message packet selected from the group consisting of a memory write complete packet, a memory read result packet, a status response packet, and an error report message packet, and wherein the physical layer signaling protocol control circuit is configured to decode the consecutive sets of symbols into consecutive sets of data bits, and form a second set of link layer bits representing the second message packet;

and,

wherein the link layer signaling protocol control circuit is configured to generate a second set of memory transaction signals based on the second set of link layer bits, and provide the second set of memory transaction signals to the bus controller.

9. The device of claim 1, wherein the link layer signaling protocol control circuit is further configured to select a memory device from a plurality of memory devices as a destination for the code word.

10. The device of claim 1, wherein the link layer signaling protocol control circuit is further configured to provide transaction timing information to the physical layer signaling protocol control circuit.

11. The device of claim 1, wherein the link layer bits comprise 24 bits, and the physical layer signaling protocol control circuit is configured to select 3 data bits from the 24 link layer bits.

12. The device of claim 1, wherein the interconnection signal lines are selected from the group consisting of an optical interface, an inductive interface, a capacitive interface and an electrical interface.

13. The device of claim 1, further comprising a simple equalizer configured to equalize the interconnection signal lines.

14. A method comprising:

transmitting messages from a memory controller using a vector signaling code, the messages selected from the group consisting of a memory write, a memory read, and a status interrogation command,

receiving a response message in the form of one or more vector signaling codes, the response message selected from the group consisting of a memory write complete, a memory read result, a status response, and an error report message,

wherein each transmitted message and received response message comprises a series of vector signaling code words, each code word communicated as symbols on a set of lines, and wherein consecutive code words of each message are synchronized by a symbol clock on the set of lines.

15. The method of claim 14, wherein the memory write and memory read operations access a contiguous block of memory of a specified size at a specified memory address.

16. The method of claim 14, wherein the set of lines comprises four bidirectional data lines and two unidirectional symbol clock lines.

17. The method of claim 16, wherein the vector signaling code communicates three binary bits on four lines using a balanced code of four levels.

18. The method of claim 14, wherein the series of vector signaling words corresponding to the response message is self-clocking.

19. The method of claim 18, wherein the self-clocking is obtained by receipt of a physical clock signal at the memory controller.

20. The method of claim 18, wherein the self-clocking is obtained by alternation of redundant code words of the vector signaling code representing the same data value.