Bias temperature instability state detection and correction

• US 9,251,890 B1
• Filed: 12/19/2014
• Issued: 02/02/2016
• Est. Priority Date: 12/19/2014
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Arsovski, Igor, Bringivijayaraghavan, Venkatraghavan, Rengarajan, Krishnan S., Agarwal, Navin
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US14/577,113
• Time in Patent Office: 410 Days
• Field of Search: 365/154, 365/156, 365/191, 365/189.07, 365/189.14, 365/189.16, 365/233.1, 365/233.11
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/06 Acceleration testing
• CPC Class Codes: G11C 29/12015 comprising clock generation or timing circuitry
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A memory device with an age-detect-and-correct (ADAC) circuit that detects skew caused by bias temperature instability fatigue (that is, bias temperature instability stress accumulated over time), and counters skew by selectively adjusting the proportion (measured temporally) of active state operation to idle state operation. Also, a memory burn-in device using a similar ADAC circuit.

Claims

1. A memory device comprising:

a set of memory circuits configured to store data by selectively being operated in one of the two following states;

idle state and active state;

a timing control module configured to selectively control the operational state of the set of memory circuits, with the timing control module including a root combinational logic location; and

an age-detect-and-correct (ADAC) circuit, connected across the root combinational logic location and including a first set of transistor(s) and a second set of transistor(s), the ADAC circuit being configured to control the timing control module to arbitrate between the idle state and the active state based upon a difference in bias temperature instability fatigue as between the first set of transistor(s) and the second set of transistor(s).

2. The memory device of claim 1 wherein:

the ADAC circuit further includes sense amplifier circuitry; and

the first set of transistor(s) and second set of transistor(s) are part of the sense amplifier circuitry.

3. The memory device of claim 2 wherein:

the first set of transistor(s) includes a first transistor pair constituted by first p-type transistor including a gate and a first n-type transistor including a gate;

the second set of transistor(s) includes a second transistor pair constituted by a second p-type transistor including a gate and a second n-type transistor including a gate; and

the first transistor pair and the second transistor pair are nominally matched, but exhibit operational mismatch, when in operation, due to a difference in bias temperature instability fatigue as between the first transistor pair and the second transistor pair.

4. The memory device of claim 3 wherein:

the gate of the first p-type transistor and the gate of the first n-type transistor are electrically coupled to each other; and

the gate of the second p-type transistor and the gate of the second n-type transistor are electrically coupled to each other.

5. The memory device of claim 4 wherein:

the first p-type transistor and the second n-type transistor are electrically connected in series with each other; and

the second p-type transistor and the first n-type transistor are electrically connected in series with each other.

6. The memory device of claim 3 wherein:

the first transistor pair experiences more bias temperature instability stress than the second transistor pair when the memory circuits are in the active state; and

the first transistor pair experiences less bias temperature instability stress than the second transistor pair when the memory circuits are in the idle state.

7. The memory device of claim 3 wherein the operational mismatch between the first transistor pair and the second transistor pair causes a propensity to settle in a preferred state that controls a manner in which the sense amplifier circuitry resolves when a set signal is turned on.

8. The memory device of claim 2 wherein the ADAC circuit further comprises:

a tri-state inverter configured to drive an input signal to the sense amplifier to a predetermined state, as a function of an input state existing when the set of memory circuits is accessed.

9. The memory device of claim 2 wherein the ADAC circuit further comprises:

a pulse generation circuit generates a pulse to equalize two input signals which are input to the sense amplifier.

10. The memory device of claim 1 wherein;

the timing control module includes an inverter chain; and

the root combinational logic location is located in the inverter chain.

11. A memory burn-in device comprising:

a set of memory circuits configured to store data by selectively being operated in one of the two following states;

idle state and active state;

a timing control module configured to selectively control the operational state of the set of memory circuits during burn-in, with the timing control module including a root combinational logic location; and

a skew detect circuit, connected across the root combinational logic location and including a first set of transistor(s) and a second set of transistor(s), the skew detect circuit being configured to control the timing control module to arbitrate between the idle state and the active state, during burn-in, based upon a difference in bias temperature instability fatigue as between the first set of transistor(s) set and the second set of transistor(s).

12. The memory burn-in device of claim 11 wherein:

the skew detect circuit further includes sense amplifier circuitry; and

the first set of transistor(s) and second set of transistor(s) are part of the sense amplifier circuitry.

13. The memory burn-in device of claim 12 wherein:

the first set of transistor(s) includes a first transistor pair constituted by first p-type transistor including a gate and a first n-type transistor including a gate;

the second set of transistor(s) includes a second transistor pair constituted by a second p-type transistor including a gate and a second n-type transistor including a gate; and

the first transistor pair and the second transistor pair are nominally matched, but exhibit operational mismatch, when in burn-in operation, due to difference in bias temperature instability fatigue as between the first transistor pair and the second transistor pair.

14. The memory burn-in device of claim 13 wherein:

the gate of the first p-type transistor and the gate of the first n-type transistor are electrically coupled to each other; and

the gate of the second p-type transistor and the gate of the second n-type transistor are electrically coupled to each other.

15. The memory burn-in device of claim 14 wherein:

the first p-type transistor and the second n-type transistor are electrically connected in series with each other; and

the second p-type transistor and the first n-type transistor are electrically connected in series with each other.

16. The memory burn-in device of claim 13 wherein:

the first transistor pair experiences more bias temperature instability stress than the second transistor pair when the memory circuits are in the active state; and

the first transistor pair experiences less bias temperature instability stress than the second transistor pair when the memory circuits are in the idle state.

17. The memory burn-in device of claim 13 wherein the operational mismatch between the first transistor pair and the second transistor pair causes a propensity to settle in a preferred state that controls a manner in which the sense amplifier circuitry resolves when a set signal is turned on.

18. The memory burn-in device of claim 12 wherein the skew detect circuit further comprises:

a pulse generation circuit generates a pulse to equalize two input signals which are input to the sense amplifier.

19. A method comprising:

starting to perform burn-in operations using a memory burn-in device that includes a set of memory circuits and a skew detection circuit, with the memory burn-in operations including an idle state and an active state;

detecting, by the skew detection circuit, which of the following two alternatives are applicable;

(i) idle state needs to be skewed, or (ii) active state needs to be skewed;

on condition that idle state needs to be skewed, then continuing burn-in operation without adjustment to an internal clock; and

on condition that active state needs to be skewed, adjusting a pulse width of an internal clock to increase the amount of time that the memory circuits are in an active state.

20. The method of claim 19 further comprising:

until burn-in operations are complete, intermittently repeating the following;

detecting, by the skew detection circuit, which of the following two alternatives are applicable;

(i) idle state needs to be skewed, or (ii) active state needs to be skewed;

on condition that idle state needs to be skewed, then continuing burn-in operation without adjustment to an internal clock; and

on condition that active state needs to be skewed, adjusting a pulse width of an internal clock to increase the amount of time that the memory circuits are in an active state.