Variable resistance nonvolatile memory device and method for writing into the same

• US 9,251,896 B2
• Filed: 04/21/2014
• Issued: 02/02/2016
• Est. Priority Date: 04/26/2013
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Inventors: Ikeda, Yuichiro, Shimakawa, Kazuhiko, Katoh, Yoshikazu, Kawai, Ken
• Primary Examiner(s): Mai, Son
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US14/257,924
• Publication Number:
  US 20140321196A1
• Time in Patent Office: 652 Days
• Field of Search: 365/148
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0092 Write characterized by the shape, e.g. form, length, amplitude of the write pulse
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor

Abstract

In a method for writing into a variable resistance nonvolatile memory device according to one aspect of the present disclosure, a verify write operation of newly applying a voltage pulse for changing a resistance state is performed on a variable resistance element which does not satisfy a determination condition for verifying that the resistance state has been changed despite application of a voltage pulse for changing the resistance state, and the determination condition in the verify write operation is relaxed when an average number of times of verify write operation, having already been performed on all or part of a plurality of variable resistance elements that are targets for write operation, exceeds a predetermined number of times.

Claims

1. A method for writing information into a variable resistance nonvolatile memory device including a variable resistance element, the method comprising:

(A) applying an initial voltage pulse to the variable resistance element for changing a resistance value of the variable resistance element;

(B) performing a first verify operation at least once after applying the initial voltage pulse, the first verify operation including

(b1) reading the resistance value of the variable resistance element,

(b2) determining whether or not the read resistance value satisfies a first determination condition, and

(b3) applying a voltage pulse to the variable resistance element when the read resistance value does not satisfy the first determination condition;

(C) stopping the first verify operation when a number of times of the first verify operation exceeds a predetermined number; and

(D) performing a second verify operation at least once when the number of times of the first verify operation exceeds the predetermined number, the second verify operation including

(d1) reading the resistance value of the variable resistance element,

(d2) determining whether or not the read resistance value satisfies a second determination condition that is looser than the first determination condition, and

(d3) applying the voltage pulse to the variable resistance element when the read resistance value does not satisfy the second determination condition.

2. The method according to claim 1, wherein:

in the first verify operation, the read resistance value is determined not to satisfy the first determination condition when the read resistance value is higher than a first threshold value,

in the second verify operation, the read resistance value is determined not to satisfy the second determination condition when the read resistance value is higher than a second threshold value, and

the second threshold value is higher than the first threshold value.

3. The method according to claim 1, wherein:

in the first verify operation, the read resistance value is determined not to satisfy the first determination condition when the read resistance value is lower than a third threshold value,

in the second verify operation, the read resistance value is determined not to satisfy the second determination condition when the read resistance value is lower than a fourth threshold value, and

the fourth threshold value is lower than the third threshold value.

4. The method according to claim 2, wherein:

the initial voltage pulse is for changing the variable resistance element from a first resistance state to a second resistance state having a lower resistance value than the first resistance state does, and

the second threshold value is lower than a reading reference resistance value that is a reading criterion for determining whether the variable resistance element is in the first resistance state or the second resistance state.

5. The method according to claim 3, wherein:

the initial voltage pulse is for changing the variable resistance element from a second resistance state to a first resistance state having a higher resistance value than the second resistance state does, and

the fourth threshold value is higher than a reading reference resistance value that is a reading criterion for determining whether the variable resistance element is the first resistance state or the second resistance state.

6. The method according to claim 1, wherein the voltage pulse is different from the initial voltage pulse in a voltage value or a pulse width.

7. The method according to claim 1, wherein the voltage pulse is same as the initial voltage pulse in a voltage value and a pulse width.

8. The method according to claim 1, further including

(E) stopping the performance of the second verify operation when the number of times of the second verify operation reaches a predetermined upper limit.

9. The method according to claim 8, further comprising:

(F) performing a third verify operation at least once after the number of times of the second verify operation reaches the predetermined upper limit, the third verify operation including

(f1) reading the resistance value of the variable resistance element,

(f2) determining whether or not the read resistance value satisfies the first determination condition, and

(f3) applying a voltage pulse to the variable resistance element when the read resistance value does not satisfy the first determination condition.

10. A variable resistance nonvolatile memory device comprising:

a memory cell array including a variable resistance element; and

pulse application circuitry operative to;

(A) apply an initial voltage pulse to the variable resistance element for changing a resistance value of the variable resistance element;

(B) perform a first verify operation at least once after applying the initial voltage pulse, the first verify operation including (b1) reading the resistance value of the variable resistance element, (b2) determining whether or not the read resistance value satisfies a first determination condition, and (b3) applying a voltage pulse to the variable resistance element when the read resistance value does not satisfy the first determination condition; and

(C) stop the first verify operation when a number of times of the first verify operation exceeds the predetermined number; and

(D) perform a second verify operation at least once when the number of times of the first verify operation exceeds a predetermined number, the second verify operation including (d1) reading the resistance value of the variable resistance element, (d2) determining whether or not the read resistance value satisfies a second determination condition that is looser than the first determination condition, (d3) applying the voltage pulse to the variable resistance element when the read resistance value does not satisfy the second determination condition.

11. The variable resistance nonvolatile memory device according to claim 10, wherein:

in the first verify operation, the read resistance value is determined not to satisfy the first determination condition when the read resistance value is higher than a first threshold value,

in the second verify operation, the read resistance value is determined not to satisfy the second determination condition when the read resistance value is higher than a second threshold value, and

the second threshold value is higher than the first threshold value.

12. The variable resistance nonvolatile memory device according to claim 10, wherein:

in the first verify operation, the read resistance value is determined not to satisfy the first determination condition when the read resistance value is lower than a third threshold value,

in the second verify operation, the read resistance value is determined not to satisfy the second determination condition when the read resistance value is lower than a fourth threshold value, and

the fourth threshold value is lower than the third threshold value.

13. The variable resistance nonvolatile memory device according to claim 11, wherein:

the initial voltage pulse is for changing the variable resistance element from a first resistance state to a second resistance state having a lower resistance value than the first resistance state does, and

the second threshold value is lower than a reading reference resistance value that is a reading criterion for determining whether the variable resistance element is in the first resistance state or the second resistance state.

14. The variable resistance nonvolatile memory device according to claim 12, wherein:

the initial voltage pulse is for changing the variable resistance element from a second resistance state to a first resistance state having a higher resistance value than the second resistance state does, and

the fourth threshold value is higher than a reading reference resistance value that is a criterion for determining whether the variable resistance element is the first resistance state or the second resistance state.

15. The variable resistance nonvolatile memory device according to claim 10, wherein the voltage pulse is different from the initial voltage pulse in a voltage value or a pulse width.

16. The variable resistance nonvolatile memory device according to claim 10, wherein the voltage pulse is same as the initial voltage pulse in a voltage value and a pulse width.

17. The variable resistance nonvolatile memory device according to claim 10, wherein the second verify operation further includes (E) stopping the performance of the second verify operation when a number of times of the second verify operation reaches a predetermined upper limit.

18. The variable resistance nonvolatile memory device according to claim 17, wherein the pulse application circuitry is further operative to:

(F) perform a third verify operation at least once after the number of times of the second verify operation reaches the predetermined upper limit, the third verify operation including (f1) reading the resistance value of the variable resistance element, (f2) determining whether or not the read resistance value satisfies the first determination condition, and (f3) applying a voltage pulse to the variable resistance element when the read resistance value does not satisfy the first determination condition.