Data scrambling based on transition characteristic of the data

• US 9,251,900 B2
• Filed: 11/30/2011
• Issued: 02/02/2016
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Sadashivappa, Dayananda Yaraganalu
• Primary Examiner(s): REVAK, CHRISTOPHER A
• Application Number:
  US13/307,610
• Publication Number:
  US 20130124781A1
• Time in Patent Office: 1,525 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method of storing data includes receiving data to be written to a memory device. The method includes selecting a scrambling operation from at least a first scrambling operation and a second scrambling operation. The scrambling operation is selected based on a transition characteristic associated with the data. The method includes scrambling the data according to the selected scrambling operation and storing the scrambled data in the memory device. Additionally, the method may include descrambling the scrambled data to produce descrambled data.

Claims

1. A method comprising:

receiving data including multiple bit groups, the data to be written to a memory device;

selecting a scrambling operation from at least a first scrambling operation and a second scrambling operation, wherein the scrambling operation is selected based on a transition characteristic based on a transition between a first bit group of the multiple bit groups that corresponds to a first threshold voltage and a second bit group of the multiple bit groups that corresponds to a second threshold voltage;

scrambling the data according to the selected scrambling operation; and

storing the scrambled data in the memory device.

2. The method of claim 1, wherein the transition characteristic includes a count of state differences between pairs of data entries within the data.

3. The method of claim 1, wherein the first bit group indicates a first value, wherein the second bit group indicates a second value, wherein the first threshold voltage corresponds to storage of the first value at a first storage element, and wherein the second threshold voltage corresponds to storage of the second value at a second storage element.

4. The method of claim 1, wherein the transition characteristic is based at least in part upon threshold voltage differences associated with at least one of a plurality of pairs of adjacent data entries within the data.

5. The method of claim 4, wherein the plurality of pairs of adjacent data entries includes:

a first plurality of pairs of data entries, wherein for each pair of the first plurality, a first data entry of the pair is to be stored in a corresponding word line and adjacent to a second data entry of the pair, the second data entry to be stored in another word line that is adjacent to the corresponding word line; and

a second plurality of pairs of data entries, wherein for each pair of the second plurality, a first data entry of the pair is to be stored in a respective word line and adjacent to a second data entry of the pair, the second data entry to be stored in the respective word line.

6. The method of claim 1, wherein the memory device includes a flash memory device.

7. The method of claim 1, wherein the memory device includes a static random access memory (SRAM) device.

8. The method of claim 1, further comprising storing an indication of the selected scrambling operation in the memory.

9. The method of claim 1, further comprising in response to a request for the data, retrieving the scrambled data and descrambling the scrambled data according to a descrambling operation that is an inverse of the selected scrambling operation to produce descrambled data.

10. The method of claim 1, wherein the first scrambling operation uses a first scrambling key and wherein the second scrambling operation uses a second scrambling key that is different from the first scrambling key.

11. The method of claim 1, wherein scrambling the data includes performing a logical combination of the data with a scrambling key associated with the selected scrambling operation.

12. The method of claim 1, wherein the first scrambling operation uses a first linear feedback shift register and wherein the second scrambling operation uses a second linear feedback shift register that is different from the first linear feedback shift register.

13. An apparatus to perform a scrambling operation, the apparatus comprising:

an interface to receive data including multiple bit groups, the data to be scrambled prior to being stored at a memory device; and

a processor to;

select a scrambling operation from at least a first scrambling operation and a second scrambling operation and to apply the scrambling operation to the data to produce scrambled data prior to writing the scrambled data to the memory device, wherein the scrambling operation is selected based on a transition characteristic based on a transition between a first bit group of the multiple bit groups that corresponds to a first threshold voltage and a second bit group of the multiple bit groups that corresponds to a second threshold voltage.

14. The apparatus of claim 13, wherein the processor is further to determine the transition characteristic by determining a count of state differences between pairs of data entries within the data.

15. The apparatus of claim 13, wherein the processor is further to determine the transition characteristic based at least in part upon threshold voltage differences associated with at least one of a plurality of pairs of adjacent data entries within the received data.

16. The apparatus of claim 15, wherein the plurality of pairs of adjacent data entries includes each pair of data entries to be stored in neighboring cells of adjacent word lines and each pair of data entries to be stored in neighboring cells of a common word line.

17. The apparatus of claim 13, wherein the memory device includes a flash memory device.

18. The apparatus of claim 13, wherein the memory device includes a static random access memory (SRAM) device.

19. An apparatus comprising:

a processor to;

select a descrambling operation from at least a first descrambling operation and a second descrambling operation, wherein the selected descrambling operation is an inverse operation of a selected scrambling operation applied to produce scrambled data from data, wherein the data includes multiple bit groups, wherein the selected scrambling operation was selected from a plurality of selectable scrambling operations based on a transition characteristic prior to storing the scrambled data, and wherein the transition characteristic is based on a transition between a first bit group of the multiple bit groups that corresponds to a first threshold voltage and a second bit group of the multiple bit groups that corresponds to a second threshold voltage; and

descramble, according to the selected descrambling operation, the scrambled data that is stored in a memory device, producing descrambled data; and

an output interface to output the descrambled data.

20. The apparatus of claim 19, further comprising a nonvolatile memory storing:

a first seed of a linear feedback shift register, the first seed associated with the first descrambling operation; and

a second seed of the linear feedback shift register, the second seed associated with the second descrambling operation.

21. A method comprising:

receiving scrambled data and a key indicator from a memory device;

selecting a descrambling operation from at least a first descrambling operation and a second descrambling operation based on the key indicator; and

descrambling the scrambled data, producing descrambled data,

wherein the selected descrambling operation is an inverse operation of a selected scrambling operation applied to produce the scrambled data from original data,

wherein the original data includes multiple bit groups, and

wherein the selected scrambling operation is selected from a plurality of selectable scrambling operations based on a transition characteristic that is based on a transition between a first bit group of the multiple bit groups that corresponds to a first threshold voltage and a second bit group of the multiple bit groups that corresponds to a second threshold voltage.

22. The method of claim 21, wherein the transition characteristic is based at least in part upon threshold voltage differences associated with at least one of a plurality of pairs of adjacent data entries within the original data.