Metal and via definition scheme

• US 9,252,048 B2
• Filed: 02/26/2014
• Issued: 02/02/2016
• Est. Priority Date: 05/14/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Yen-Cheng, Shih, Chih-Tsung, Yu, Shinn-Sheng, Chen, Jeng-Horng, Yen, Anthony
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US14/191,169
• Publication Number:
  US 20150072519A1
• Time in Patent Office: 706 Days
• Field of Search: 438/626, 438/638
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31133 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76846 Layer combinations

Abstract

A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.

Claims

1. A method, comprising:

defining a photoresist layer over a first dielectric layer, wherein the first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer;

forming a spacer layer over the photoresist and the first dielectric layer, wherein the spacer layer has a first opening that has a via width and the first opening is disposed directly above a via location;

forming a metal trench with a metal width in the first dielectric layer, wherein the metal width at the via location is greater than the via width; and

forming a via hole with the via width at the via location in the second dielectric layer.

2. The method of claim 1, wherein forming the spacer layer comprises depositing the spacer layer over the photoresist layer and the first dielectric layer by an atomic layer deposition (ALD).

3. The method of claim 2, wherein forming the spacer layer further comprises etching the spacer layer to form the first opening with the via width.

4. The method of claim 1, wherein each of the first dielectric layer and the second dielectric layer comprise low-k dielectric material or SiO₂.

5. The method of claim 1, wherein the spacer layer is generally conformal and gap filling.

6. The method of claim 1, wherein defining the photoresist comprises forming a second opening in the photoresist layer directly above the via location and the second opening has an aspect ratio ranging from about 1 to about 1.6.

7. The method of claim 6, wherein defining the photoresist further comprises forming a third opening in the photoresist layer not directly above the via location and the third opening has an aspect ratio ranging from about 1.4 to about 2.5.

8. The method of claim 1, wherein the metal width at the via location is greater than the metal width away from the via location from about 10% to about 50%.

9. The method of claim 1, further comprising etching the first dielectric layer to form a second opening having a width matching the via width at the via location.

10. The method of claim 9, further comprising removing the spacer layer after etching the first dielectric layer.

11. The method of claim 10, wherein removing the spacer layer is performed by a wet etching process using a H₃PO₄ solution at about 165°

C.

12. The method of claim 10, further comprising removing the photoresist layer after removing the spacer layer.

13. The method of claim 1, further comprising:

forming a barrier layer in the metal trench and the via hole, wherein the barrier layer comprises Ta, TaN, TiN, or any combination thereof;

forming a seed layer over the barrier layer;

filling a metal layer in the metal trench and the via hole; and

performing a planarizing process to remove a portion of the metal layer.

14. The method of claim 1, wherein a dry etching or a plasma etching process is used to form the metal trench and the via hole.

15. A method, comprising:

defining a photoresist layer over a first dielectric layer, wherein the first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer;

depositing a spacer layer over the photoresist layer and the first dielectric layer; and

etching the spacer layer to form a first opening with a via width wherein the first opening is disposed directly above a via location;

etching the first dielectric layer to form a second opening with a width matching the via width at the via location;

forming a metal trench with a metal width in the first dielectric layer, wherein the metal width at the via location is greater than the via width; and

forming a via hole with the via width at the via location in the second dielectric layer.

16. The method of claim 15, wherein the spacer layer is deposited by an atomic layer deposition (ALD) process and the spacer layer is generally conformal and gap filling.

17. The method of claim 15, wherein each of the first dielectric layer and the second dielectric layer comprise low-k dielectric material or SiO₂.

18. The method of claim 15, wherein defining the photoresist comprises forming a second opening in the photoresist layer directly above the via location and the second opening has an aspect ratio ranging from about 1 to about 1.6.

19. The method of claim 15, further comprising removing the photoresist layer by O₂ ash process.

20. A method, comprising:

defining a photoresist layer over a first dielectric layer, wherein the first dielectric layer is disposed over an etch stop layer, the etch stop layer is disposed over a second dielectric layer, and the first dielectric layer and the second dielectric layer comprise low-k dielectric material or SiO₂;

forming a spacer layer over the photoresist and the first dielectric layer, wherein the spacer layer has a first opening that has a via width, the first opening is disposed directly above a via location, and the spacer layer comprises SiN;

etching the first dielectric layer to form a second opening with a width matching the via width at the via location;

removing the spacer layer after etching the first dielectric layer;

forming a metal trench with a metal width in the first dielectric layer, wherein the metal width at the via location is greater than the via width;

forming a via hole with the via width at the via location in the second dielectric layer; and

removing the photoresist layer.