Semiconductor device and method of forming an interconnect structure with conductive material recessed within conductive ring over surface of conductive pillar

• US 9,252,094 B2
• Filed: 04/30/2011
• Issued: 02/02/2016
• Est. Priority Date: 04/30/2011
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Stats Chippac Limited
• Inventors: Choi, DaeSik, Park, Sang Mi
• Primary Examiner(s): Le, Thao X
• Assistant Examiner(s): DYKES, LAURA M
• Application Number:
  US13/098,448
• Publication Number:
  US 20120273938A1
• Time in Patent Office: 1,739 Days
• Field of Search: 257/737, 438/614
• US Class Current: 1/1
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 2224/0332 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/03474 Multilayer masks
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/0566 Iron [Fe] as principal constituent
• CPC Class Codes: H01L 2224/05666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/10145 : Flow barriers
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/1133 : in solid form
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1145 : Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 : Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 : Electroplating
• CPC Class Codes: H01L 2224/11464 : Electroless plating
• CPC Class Codes: H01L 2224/1161 : Physical or chemical etching
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/11903 : using different masks
• CPC Class Codes: H01L 2224/13014 : being circular or elliptic
• CPC Class Codes: H01L 2224/13016 : in side view
• CPC Class Codes: H01L 2224/13019 : at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13076 : being mutually engaged together, e.g. through inserts
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 : Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/8114 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81411 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H01L 2924/3841 : Solder bridging

Abstract

A semiconductor device has a semiconductor die with a first conductive layer formed over an active surface of the semiconductor die. An insulation layer is formed over the active surface of the semiconductor die. A second conductive layer is conformally applied over the insulating layer and first conductive layer. Conductive pillars are formed over the first conductive layer. Conductive rings are formed around a perimeter of the conductive pillars. A conductive material is deposited over the surface of the conductive pillars within the conductive rings. A substrate has a third conductive layer formed over a surface of the substrate. The semiconductor die is mounted to a substrate with the third conductive layer electrically connected to the conductive material within the conductive rings. The conductive rings inhibit outward flow of the conductive material from under the conductive pillars to prevent electrical bridging between adjacent conductive pillars.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor die including a first conductive layer formed over a surface of the semiconductor die;

forming a first insulating layer over the surface of the semiconductor die and first conductive layer;

conformally applying a second conductive layer over the first insulating layer and first conductive layer;

forming a second insulating layer over the second conductive layer;

forming a plurality of conductive pillars within the second insulating layer;

forming a third insulating layer over the second insulating layer and conductive pillars;

removing a ring-shaped portion of the third insulating layer around a perimeter of the conductive pillars;

forming a plurality of conductive rings within the removed ring-shaped portion of the third insulating layer over and around the perimeter of the conductive pillars;

removing a circular portion of the third insulating layer over the conductive pillars within the conductive rings;

depositing a conductive material over the conductive pillars within the conductive rings; and

removing remaining portions of the second and third insulating layers.

2. The method of claim 1, further including:

providing a substrate;

forming a third conductive layer over a surface of the substrate;

forming a fourth insulating layer over the surface of the substrate and third conductive layer;

forming a plurality of bumps over the third conductive layer; and

disposing the semiconductor die over the substrate with the bumps bonded to the conductive material over the conductive pillars within the conductive rings.

3. The method of claim 2, wherein the conductive rings inhibit outward flow of the conductive material and bumps from under the conductive pillars.

4. The method of claim 2, further including disposing the semiconductor die over the substrate by reflowing the bumps and conductive material.

5. The method of claim 2, further including disposing the semiconductor die over the substrate so that the conductive rings contact the fourth insulating layer or the substrate.

6. The method of claim 1, further including utilizing laser direct ablation to remove a portion of the second insulating layer in order to form the conductive pillars.

7. The method of claim 1, further including:

providing a substrate;

forming a third conductive layer over a surface of the substrate;

forming a fourth insulating layer over the surface of the substrate and third conductive layer; and

disposing the semiconductor die over the substrate with the third conductive layer bonded to the conductive material.

8. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a first conductive layer over a surface of the semiconductor die;

forming a conductive pillar over the first conductive layer;

forming a first insulating layer over a surface of the conductive pillar;

forming a ring-shaped opening in the first insulating layer around a perimeter of the conductive pillar;

forming a second conductive layer in the ring-shaped opening in the first insulating layer;

removing the first insulating layer over the surface of the conductive pillar; and

forming a first conductive material to fill an area over the surface of the conductive pillar within a height of the second conductive layer with the first conductive material terminating within a footprint of the conductive pillar providing a substrate;

forming a third conductive layer over a surface of the substrate;

forming a second insulating layer over the surface of the substrate and third conductive layer;

forming a plurality of bumps over the third conductive layer; and

disposing the semiconductor die over the substrate with the bumps bonded to the first conductive material.

9. The method of claim 8, further including disposing the semiconductor die over the substrate so that the second conductive layer contacts the second insulating layer or the substrate.

10. The method of claim 8, wherein the second conductive layer reduces outward flow of the first conductive material from under the conductive pillars.

11. The method of claim 8, further including disposing the semiconductor die over the substrate by reflowing the first conductive material.

12. The method of claim 8, wherein forming the conductive pillar includes:

forming a third insulating layer over the surface of the semiconductor die;

forming an opening in the third insulating layer; and

depositing a second conductive material in the opening of the third insulating layer to form the conductive pillar.

13. A method of making a semiconductor device, comprising:

providing a semiconductor die;

forming a conductive pillar over the semiconductor die;

depositing a first conductive layer over a perimeter of a surface of the conductive pillar; and

forming a first conductive material to fill an area over the surface of the conductive pillar within a height of the first conductive layer providing a substrate;

forming a second conductive layer over a surface of the substrate;

forming a first insulating layer over the surface of the substrate and second conductive layer;

forming a plurality of bumps over the second conductive layer; and

disposing the semiconductor die over the substrate with the bumps bonded to the first conductive material.

14. The method of claim 13, further including disposing the semiconductor die over the substrate so that the first conductive layer contacts the first insulating layer or the substrate.

15. The method of claim 13, wherein the first conductive layer reduces outward flow of the first conductive material.

16. The method of claim 13, wherein forming the conductive pillar includes:

forming a second insulating layer over the semiconductor die;

forming an opening in the second insulating layer; and

depositing a second conductive material in the opening of the second insulating layer to form the conductive pillar.

17. The method of claim 16, wherein forming the first conductive layer includes:

forming a third insulating layer over the first insulating layer and conductive pillar;

forming an opening in the third insulating layer around the perimeter of the surface of the conductive pillar; and

depositing a third conductive material in the opening of the third insulating layer to form the first conductive layer.