Semiconductor device and method for producing semiconductor device

• US 9,252,190 B2
• Filed: 09/10/2014
• Issued: 02/02/2016
• Est. Priority Date: 11/13/2013
• Status: Active Grant

• Current Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Original Assignee: Unisantis Electronics Singapore Pte. Ltd. (NewScope Group Holdings AG)
• Inventors: Masuoka, Fujio, Nakamura, Hiroki
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/482,750
• Publication Number:
  US 20150129825A1
• Time in Patent Office: 510 Days
• Field of Search: 257/288, 257/350, 257/401, 257/618, 438/149, 438/156, 438/197, 438/279, 438/286
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/021 Formation of switching materials, e.g. deposition of layers
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/235 between different crystalline phases, e.g. cubic and hexagonal
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8613 Heating or cooling means other than resistive heating electrodes, e.g. heater in parallel
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A semiconductor device according to the present invention comprises a first pillar-shaped semiconductor layer, a gate insulating film formed around the first pillar-shaped semiconductor layer, a gate electrode made of a metal and formed around the gate insulating film, a gate line made of a metal and connected to the gate electrode, a second gate insulating film formed around an upper portion of the first pillar-shaped semiconductor layer, a first contact made of a second metal and formed around the second gate insulating film, a second contact which is made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer, a second diffusion layer formed in a lower portion of the first pillar-shaped semiconductor layer, a pillar-shaped resistance-changing layer formed on the second contact, a reset gate insulating film that surrounds the pillar-shaped resistance-changing layer, and a reset gate that surrounds the reset gate insulating film.

Claims

1. A semiconductor device comprising:

a first pillar-shaped semiconductor layer;

a gate insulating film around the first pillar-shaped semiconductor layer;

a gate electrode made of a metal around the gate insulating film;

a gate line made of a metal and connected to the gate electrode;

a second gate insulating film around an upper portion of the first pillar-shaped semiconductor layer;

a first contact made of a second metal and around the second gate insulating film;

a second contact made of a third metal and which connects an upper portion of the first contact to an upper portion of the first pillar-shaped semiconductor layer;

a diffusion layer in a lower portion of the first pillar-shaped semiconductor layer;

a pillar-shaped resistance-changing layer on the second contact;

a reset gate insulating film that surrounds the pillar-shaped resistance-changing layer; and

a reset gate that surrounds the reset gate insulating film.

2. The semiconductor device according to claim 1, further comprising a lower electrode below the pillar-shaped resistance-changing layer.

3. The semiconductor device according to claim 2, wherein the lower electrode is made of titanium nitride.

4. The semiconductor device according to claim 1, wherein the reset gate is made of titanium nitride.

5. The semiconductor device according to claim 1, wherein the reset gate insulating film is a nitride film.

6. The semiconductor device according to claim 1, wherein the resistance-changing layer is reset by an electric current flowing through the reset gate.

7. The semiconductor device according to claim 1, wherein the second metal of the first contact has a work function of 4.0 eV to 4.2 eV.

8. The semiconductor device according to claim 1, wherein the second metal of the first contact has a work function of 5.0 eV to 5.2 eV.

9. The semiconductor device according to claim 1 further comprising:

a fin-shaped semiconductor layer on a semiconductor substrate; and

a first insulating film around the fin-shaped semiconductor layer,

wherein the first pillar-shaped semiconductor layer is formed-on the fin-shaped semiconductor layer,

the gate insulating film is around the gate electrode and the gate line and on bottom portions of the gate electrode and the gate line,

the gate line extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and

the diffusion layer further resides in the fin-shaped semiconductor layer.

10. The semiconductor device according to claim 9, wherein the diffusion layer further resides in the semiconductor substrate.

11. The semiconductor device according to claim 9, further comprising a contact line parallel to the gate line and connected to the diffusion layer.

12. The semiconductor device according to claim 11, further comprises:

a second pillar-shaped semiconductor layer on the fin-shaped semiconductor layer; and

a contact electrode made of a metal and around the second pillar-shaped semiconductor layer,

wherein the contact line made of a metal and extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer connected to the contact electrode extends,

the diffusion layer is in the fin-shaped semiconductor layer and in a lower portion of the second pillar-shaped semiconductor layer, and

the contact electrode is connected to the diffusion layer.

13. The semiconductor device according to claim 12, wherein the gate insulating film is between the second pillar-shaped semiconductor layer and the contact electrode.

14. The semiconductor device according to claim 13, wherein the gate insulating film is around the contact electrode and the contact line.

15. The semiconductor device according to claim 12, wherein a width of the second pillar-shaped semiconductor layer in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends is equal to a width of the fin-shaped semiconductor layer in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.

16. The semiconductor device according to claim 12, wherein an outer width of the contact electrode is equal to a width of the contact line.

17. The semiconductor device according to claim 9, wherein an outer width of the gate electrode is equal to a width of the gate line, and

a width of the first pillar-shaped semiconductor layer in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends is equal to a width of the fin-shaped semiconductor layer in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.

18. The semiconductor device according to claim 1, wherein the first pillar-shaped semiconductor layer is on a semiconductor substrate, the gate insulating film is around the gate electrode and the gate line and on bottom portions of the gate electrode and the gate line, and the diffusion layer further resides in the semiconductor substrate.