Transistor and method of fabricating the same

• US 9,252,222 B2
• Filed: 07/15/2015
• Issued: 02/02/2016
• Est. Priority Date: 06/14/2013
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Cho, Sung Haeng, Park, Sang-Hee, Hwang, Chi-Sun
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/800,251
• Publication Number:
  US 20150318363A1
• Time in Patent Office: 202 Days
• Field of Search: 257/66, 257/401, 438/151
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41758 for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular H01L29/41733 - H01L29/4175 take precedence
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

Provided is a transistor. The transistor includes: a substrate; a semiconductor layer provided on the substrate and having one side vertical to the substrate and the other side facing the one side; a first electrode extending along the substrate and contacting the one side of the semiconductor layer; a second electrode extending along the substrate and contacting the other side of the semiconductor layer; a conductive wire disposed on the first electrode and spaced from the second electrode; a gate electrode provided on the semiconductor layer; and a gate insulating layer disposed between the semiconductor layer and the gate electrode, wherein the semiconductor layer, the first electrode, and the second electrode have a coplanar.

Claims

1. A method of fabricating a transistor, the method comprising:

providing a substrate including a semiconductor layer;

forming a gate insulating layer and a gate electrode at a position corresponding to a core of the semiconductor layer;

forming an interlayer insulating layer covering the gate electrode and exposing both sides of the semiconductor layer;

forming an electrode layer extending along the substrate and contacting the both sides of the semiconductor layer;

forming a conductive layer covering the electrode layer;

forming a first electrode and a second electrode spaced from the first electrode by patterning the electrode layer; and

forming a conductive line on the first electrode by removing the conductive layer on the second electrode,

wherein the first electrode contacts one side of the semiconductor layer and the second electrode contacts the other side of the semiconductor layer; and

the semiconductor layer, the first electrode, and the second electrode have a coplanar level surface.

2. The method of claim 1, wherein a lowermost surface of the electrode layer adjacent the substrate has the same level as a bottom surface of the semiconductor layer adjacent the substrate.

3. The method of claim 1, wherein the first electrode has a symmetric form to the second electrode.

4. The method of claim 1, wherein the patterning of the electrode layer comprises removing the electrode layer on a position corresponding to the gate electrode.

5. The method of claim 1, wherein the forming of the interlayer insulating layer comprises:

forming an insulating layer covering the substrate, the semiconductor layer, and the gate electrode;

forming a channel region, a source region, and a drain region on the semiconductor layer by thermally-treating the insulating layer; and

removing a portion of the insulating layer to expose the source region and the drain region,

wherein one of the source region and the drain region extends from the one side of the semiconductor layer and the other one extends from the other side of the semiconductor layer, and the channel region is disposed between the source region and the drain region.

6. The method of claim 1, further comprising:

forming a passivation layer covering the conductive line, the interlayer insulating layer, and the second electrode; and

partially exposing the conductive line by forming an opening penetrating the passivation layer.