Semiconductor structures with coplanar recessed gate layers and fabrication methods

• US 9,252,238 B1
• Filed: 08/18/2014
• Issued: 02/02/2016
• Est. Priority Date: 08/18/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.), Lam Research Corporation
• Original Assignee: GlobalFoundries, Inc., Lam Research Corporation
• Inventors: Trevino, Kristina, Liu, Yuan-Hung, Wells, Gabriel Padron, Zhang, Xing, Wong, Hoong Shing, Han, Taejoon, Kamarthy, Gowri, Maeng, Chang Ho, Orain, Isabelle, Upadhyaya, Ganesh
• Primary Examiner(s): Roman, Angel
• Application Number:
  US14/461,887
• Publication Number:
  US 20160049495A1
• Time in Patent Office: 533 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31122 of layers not containing Si, e.g. PZT, Al2O3
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Claims

1. A method comprising:

fabricating a semiconductor structure, the fabricating comprising;

providing a gate structure over a semiconductor substrate, the gate structure comprising multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers;

recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, wherein upper surfaces of the recessed, multiple conformal gate layers are coplanar; and

removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

2. The method of claim 1, wherein the providing comprises providing at least one conformal gate layer of the multiple conformal gate layers, and the recessing comprises recessing a portion of the at least one conformal gate layer of the multiple conformal gate layers, prior to removing the gate material disposed within the gate structure.

3. The method of claim 1, wherein the multiple conformal gate layers comprise a gate dielectric layer disposed conformally within the gate structure, and a work-function layer disposed conformally above the gate dielectric layer, and the recessing comprises recessing a portion of the work-function layer from within the gate structure, prior to recessing the gate dielectric layer.

4. The method of claim 3, wherein the recessed, multiple conformal gate layer comprises one of a recessed work-function layer or a recessed gate dielectric layer.

5. The method of claim 3, wherein the recessing comprises performing a first recessing process, and performing a second recessing process, the first recessing process being performed over the work-function layer, and the second recessing process being performed over the gate dielectric layer.

6. The method of claim 5, wherein the first recessing process being performed at a first time interval, and the method further comprises performing the second recessing process at a second time interval, the first time interval and the second time interval being different time intervals, and the second time interval being longer than the first time interval.

7. The method of claim 5, wherein the recessing further comprises performing the first recessing process of the work-function layer, and performing the second recessing process of the gate dielectric layer using same etching chemistries.

8. The method of claim 7, wherein the same etching chemistries are performed employing boron trichloride gas.

9. The method of claim 3, wherein the gate dielectric layer comprises a high-k gate dielectric layer, and wherein the work-function layer comprises a metal work-function layer.

10. The method of claim 1, wherein the method comprises recessing of the multiple conformal gate layers being performed using a first etching chemistry, and removing of the gate material being performed using a second etching chemistry, the first etching chemistry and the second etching chemistry employing different etching chemistries.

11. The method of claim 10, wherein the first etching chemistry being performed employing boron trichloride, and the second etching chemistry being performed employing silicon tetrachloride.

12. The method of claim 1, wherein the gate material comprises a metal gate material.

13. A structure comprising:

a semiconductor structure, the semiconductor structure comprising;

a semiconductor substrate;

a gate structure disposed over the semiconductor substrate, the gate structure comprising recessed, multiple conformal gate layers, wherein multiple conformal gate layers are recessed below an upper surface of the gate structure, and upper surfaces of the recessed, multiple conformal gate layers are coplanar; and

a recessed gate material disposed within the recessed, conformal gate layers, wherein an upper surface of the recessed gate material is coplanar with the upper surfaces of the recessed, multiple conformal gate layers.

14. The structure of claim 13, wherein the recessed, multiple conformal gate layers comprise a recessed gate dielectric layer, and wherein the structure further comprises a recessed work-function layer disposed over the recessed gate dielectric layer, an upper surface of the gate dielectric layer being coplanar with an upper surface of the recessed work-function layer.

15. The structure of claim 14, wherein the recessed gate dielectric layer comprises a high-k gate dielectric layer, and wherein the recessed work-function layer comprises a metal work-function layer.

16. The structure of claim 13, wherein the recessed gate material comprises a metal gate material.

17. A structure comprising:

a semiconductor structure, the semiconductor structure comprising;

a semiconductor substrate;

a gate structure disposed over the semiconductor substrate, the gate structure comprising recessed, multiple conformal gate layers, wherein multiple conformal gate layers are recessed below an upper surface of the gate structure, and upper surfaces of the recessed, multiple conformal gate layers are coplanar; and

a gate material disposed within the recessed, multiple conformal gate layers, wherein an uppermost surface of the gate material is disposed above the upper surface of the gate structure.

18. The structure of claim 17, wherein the recessed, multiple conformal gate layers comprise a recessed gate dielectric layer, and wherein the structure further comprises a recessed work-function layer disposed over the recessed gate dielectric layer, an upper surface of the gate dielectric layer being coplanar with an upper surface of the recessed work-function layer.

19. The structure of claim 17, wherein the recessed gate dielectric layer comprises a high-k gate dielectric layer, and wherein the recessed work-function layer comprises a metal work-function layer.

20. The structure of claim 17, wherein the gate material comprises a metal gate material, and the structure further comprises the upper surface of the gate material being disposed above the upper surface of the recessed, at least one conformal gate layer.