Multiple semiconductor device trenches per cell pitch
First Claim
1. A semiconductor device, comprising:
- a plurality of field plate trenches formed in a semiconductor substrate;
a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and
a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch,wherein at least some of the device cells have more than one gate trench per cell pitch,wherein at least some of the device cells that have more than one gate trench per cell pitch include only a single type of gate trench that comprises a gate conductor disposed in a gate trench.
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Accused Products
Abstract
A semiconductor device includes a plurality of field plate trenches formed in a semiconductor substrate, a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches, and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench. Each device cell includes a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch. At least some of the device cells have more than one gate trench per cell pitch.
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Citations
26 Claims
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1. A semiconductor device, comprising:
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a plurality of field plate trenches formed in a semiconductor substrate; a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch, wherein at least some of the device cells have more than one gate trench per cell pitch, wherein at least some of the device cells that have more than one gate trench per cell pitch include only a single type of gate trench that comprises a gate conductor disposed in a gate trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A semiconductor device, comprising:
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a plurality of field plate trenches formed in a semiconductor substrate; a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch, wherein at least some of the device cells have more than one gate trench per cell pitch, wherein the field plate trenches have an extension in every direction in parallel to a first main surface of the semiconductor substrate, which is smaller than a maximum extension in a direction perpendicular to the first main surface, wherein the first doped region of the device cells is a transistor source region, wherein the second doped region of the device cells is a transistor body region, and wherein the body region of the device cells that have more than one gate trench per cell pitch is electrically contacted within the device cells only through a field plate in the field plate trenches.
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23. A semiconductor device, comprising:
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a plurality of field plate trenches formed in a semiconductor substrate; a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch, wherein at least some of the device cells have more than one gate trench per cell pitch, wherein the field plate trenches have an extension in every direction in parallel to a first main surface of the semiconductor substrate, which is smaller than a maximum extension in a direction perpendicular to the first main surface, wherein at least two of the gate trenches of the device cells that have more than one gate trench per cell pitch intersect within the same device cell. - View Dependent Claims (24)
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25. A semiconductor device, comprising:
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a plurality of field plate trenches formed in a semiconductor substrate; a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch, wherein at least some of the device cells have more than one gate trench per cell pitch, wherein the field plate trenches have an extension in every direction in parallel to a first main surface of the semiconductor substrate, which is smaller than a maximum extension in a direction perpendicular to the first main surface, wherein the gate trenches of the device cells that have more than one gate trench per cell pitch are non-intersecting within the same device cell so that the second doped region extends continuously within each device cell to the end of the device cell without interruption by the gate trenches, wherein the second doped region of the device cells that have more than one gate trench per cell pitch is electrically contacted within the device cells only through a field plate in the field plate trenches.
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26. A semiconductor device, comprising:
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a plurality of field plate trenches formed in a semiconductor substrate; a plurality of gate trenches formed in the semiconductor substrate and spaced apart from the field plate trenches; and a plurality of device cells having a cell pitch defined by a distance from one side of a field plate trench to the same side of an adjacent field plate trench, each device cell comprising a first doped region of a first conductivity type and a second doped region of a second conductivity type adjacent the first doped region in a part of the semiconductor substrate disposed between the adjacent field plate trenches that define the cell pitch, wherein at least some of the device cells have more than one gate trench per cell pitch, wherein the field plate trenches have an extension in every direction in parallel to a first main surface of the semiconductor substrate, which is smaller than a maximum extension in a direction perpendicular to the first main surface, wherein at least some of the device cells that have more than one gate trench per cell pitch include a first type of gate trench and a second type of gate trench, wherein the first type of gate trench comprises a gate conductor disposed in a gate trench and electrically insulated from the first and second doped regions of the device cell, and wherein the second type of gate trench comprises a gate conductor disposed in a gate trench and electrically connected to the first and second doped regions of the device cell, wherein the gate trenches of the first type have a different geometry than the gate trenches of the second type within the same device cell.
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Specification