Wide band gap semiconductor device and method for producing the same

• US 9,252,266 B2
• Filed: 06/20/2013
• Issued: 02/02/2016
• Est. Priority Date: 04/17/2008
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Iwamuro, Noriyuki
• Primary Examiner(s): Menz, Laura
• Assistant Examiner(s): CHAN, CANDICE
• Application Number:
  US13/922,740
• Publication Number:
  US 20130285072A1
• Time in Patent Office: 957 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/452 on AIII-BV compounds
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7839 with Schottky drain or source contact

Abstract

A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and second trench in a source electrode part (Schottky diode) are disposed close to each other, and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a small wide band gap semiconductor device which is low in on-resistance and loss. Electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage and increase avalanche breakdown tolerance at turning-off time.

Claims

1. A wide band gap semiconductor device comprising:

a silicon carbide semiconductor substrate;

a second conductivity type silicon carbide semiconductor layer having a high impurity concentration and disposed on one principal surface of the semiconductor substrate;

a second conductivity type silicon carbide drift layer having a low impurity concentration and disposed on the second conductivity type silicon carbide semiconductor layer;

a first conductivity type silicon carbide base layer disposed on the drift layer;

a second conductivity type silicon carbide source region selectively disposed on a principal surface of the base layer;

a first trench having a depth extending from a principal surface of the source region to reach the drift layer;

a gate insulating film lining the first trench;

a control electrode which is filled in the first trench, inside the gate insulating film, so as to be located in a position facing the source region, the base layer and the drift layer;

a second trench provided near the first trench and having a depth extending from the principal surface of the base layer to reach the drift layer so as to be deeper than the first trench;

a first main electrode which is disposed in the second trench to form a Schottky junction between the first main electrode and a surface of the drift layer located in the second trench so that the first main electrode covers the principal surface of the source region and the principal surface of the base layer in common;

third trenches each of which has a depth extending from the other principal surface of the silicon carbide semiconductor substrate to reach the second conductivity type silicon carbide semiconductor layer having the high impurity concentration; and

a second main electrode which is electrically connected to inner surfaces of the third trenches and the other principal surface of the silicon carbide semiconductor substrate.

2. A wide band gap semiconductor device according to claim 1, further comprising a first conductivity type region being in contact with a bottom of the second trench.

3. A wide band gap semiconductor device according to claim 1, wherein the distance between central lines of the first and second trenches is not longer than 10 μ

m.

4. A method of producing a wide band gap semiconductor device as defined in claim 1, comprising the steps of:

grinding the other principal surface of the semiconductor substrate to provide the semiconductor substrate as a thin layer before forming the second main electrode;

forming the third trenches on the other principal surface of the ground semiconductor substrate; and

forming the second main electrode.