Gate stack and contact structure

• US 9,252,273 B2
• Filed: 01/03/2014
• Issued: 02/02/2016
• Est. Priority Date: 01/03/2014
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Zang, Hui
• Primary Examiner(s): Li, Meiya
• Assistant Examiner(s): Albrecht, Peter M
• Application Number:
  US14/147,181
• Publication Number:
  US 20150194517A1
• Time in Patent Office: 760 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02057 Cleaning during device manufacture
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A process for fabrication of semiconductor devices, particularly fin-shaped Field Effect Transistors (FinFETs), having a low contact horizontal resistance and a resulting device are provided. Embodiments include: providing a substrate having source and drain regions separated by a gate region; forming a gate electrode having a first length on the gate region; forming an epitaxy layer on the source and drain regions; forming a contact layer having a second length, longer than the first length, at least partially on the epitaxy layer; and forming an oxide layer on top and side surfaces of the contact layer for at least the first length.

Claims

1. A method comprising:

providing a substrate having a source region and a drain region separated along a first direction by a gate region, the first direction being perpendicular to a thickness direction of the substrate;

forming a gate electrode on the gate region and having a first length along a second direction, the second direction being perpendicular to both the thickness direction of the substrate and the first direction;

forming an epitaxy layer on the source region and the drain region;

forming a first contact layer at least partially on the epitaxy layer and having a second length along the second direction, the second length being longer than the first length; and

forming an oxide layer on a top surface and side surfaces of the first contact layer for at least the first length.

2. The method according to claim 1, comprising:

forming the gate electrode by;

forming a polycrystalline silicon gate on the gate region;

forming a nitride layer on at least side surfaces of the polycrystalline silicon gate;

removing the polycrystalline silicon gate to form a recess;

forming a high-k dielectric in the recess;

forming a metal gate on the high-k dielectric in the recess; and

reducing a height of the metal gate; and

forming a second contact layer on the metal gate for the first length.

3. The method according to claim 2, further comprising:

forming the nitride layer on a top surface of the polycrystalline silicon gate; and

removing the nitride layer from the top surface of the polycrystalline silicon gate prior to removing the polycrystalline silicon gate.

4. The method according to claim 1, comprising:

forming the gate electrode by;

forming a high-k dielectric layer in the gate region;

forming a dummy gate on the high-k dielectric layer;

annealing, prior to providing the oxide layer on the top surface of the first contact layer;

removing the dummy gate to form a recess;

forming a replacement metal gate on the high-k dielectric layer in the recess; and

reducing a height of the metal gate; and

providing a second contact layer on the replacement metal gate for the first length.

5. The method according to claim 4, wherein the high-k dielectric layer is at side surfaces and a bottom surface of the dummy gate, the method further comprising:

forming a nitride layer on side surfaces of the high-k dielectric layer.

6. The method according to claim 5, further comprising:

forming the first contact layer and the second contact layer of tungsten (W); and

forming the dummy gate of titanium nitride (TiN) and polycrystalline silicon.

7. The method according to claim 1, comprising:

forming a low-k dielectric layer on the oxide layer and having a first portion and a second portion in the drain region and the source region, respectively; and

reducing a height of the gate electrode; and

forming a second contact layer between the first portion and the second portion of the low-k dielectric layer and on the gate electrode, the second contact layer extending over the drain region and the source region over the first length

and being separated from the first contact layer by the oxide layer.

8. The method according to claim 1, further comprising:

forming a shallow trench isolation (STI) region in the substrate horizontally beyond the epitaxy layer, the first contact layer extending over the STI region;

forming a vertical portion of the first contact layer over the STI region; and

forming a second contact layer on the gate electrode.

9. A method comprising:

providing a substrate having a source region and a drain region separated along a first direction by a gate region, the first direction being perpendicular to a thickness direction of the substrate;

forming a gate electrode on the gate region and having a first length along a second direction and a first height, the second direction being perpendicular to both the thickness direction of the substrate and the first direction;

forming an epitaxy layer on the source region and the drain region;

forming a shallow trench isolation (STI) region in the substrate horizontally beyond the epitaxy layer;

forming a tungsten (W) contact layer at least partially on the epitaxy layer and having a second length along the second direction, the second length being longer than the first length, the tungsten contact layer having a second height less than the first height, the tungsten contact layer extending horizontally over the STI region and comprising a vertical portion over the STI region, the tungsten contact layer being a first contact layer; and

forming an oxide layer on a top surface and side surfaces of the first contact layer for at least the first length.

10. The method according to claim 9, comprising:

forming the gate electrode by;

forming a polycrystalline silicon gate on the gate region;

forming a nitride layer on side surfaces and a top surface of the polycrystalline silicon gate;

removing the nitride layer from the top surface of the polycrystalline silicon gate;

removing, after removal of the nitride layer from the top surface of the polycrystalline silicon gate, the polycrystalline silicon gate to form a recess;

forming a high-k dielectric in the recess;

forming a titanium carbide (TiC) work function metal on the high-k dielectric in the recess;

forming a metal gate on the work function metal in the recess, the metal gate having a height; and

reducing the height of the metal gate to the first height; and

forming a second contact layer on the metal gate for the first length.

11. The method according to claim 9, comprising:

forming the gate electrode by;

forming a high-k dielectric layer in the gate region;

forming a dummy gate on the high-k dielectric layer, the dummy gate comprising titanium nitride (TiN) and polycrystalline silicon;

annealing, prior to providing the oxide layer on the top surface and the side surfaces of the first contact layer;

removing the dummy gate to form a recess;

forming a titanium carbide (TiC) work function metal layer in the recess;

forming a replacement metal gate on the work function metal layer in the recess;

reducing a height of the metal gate to the first height; and

forming a second contact layer on the metal gate for the first length; and

forming a nitride layer on side surfaces of the high-k dielectric layer.

12. The method according to claim 9, comprising:

forming a low-k dielectric layer on the oxide layer and having a first portion and a second portion in the drain region and the source region, respectively; and

forming a second contact layer on the gate electrode and between the first portion and the second portion of the low-k dielectric layer, the second contact layer extending over the drain region and the source region over the first length and being separated from the first contact layer by the oxide layer.